Technical Library | 2012-04-26 18:52:37.0
First presented at IPC Apex Expo 2012. The reliability, as tested by thermal cycling, of printed wire boards (PWB) are established by three variables; copper quality, material robustness and design. The copper quality was most influential and could be eva
Technical Library | 2018-05-09 22:15:29.0
Creep corrosion on printed circuit boards (PCBs) is the corrosion of copper metallization and the spreading of the copper corrosion products across the PCB surfaces to the extent that they may electrically short circuit neighboring features on the PCB. The iNEMI technical subcommittee on creep corrosion has developed a flowers-of-sulfur (FOS) based test that is sufficiently well developed for consideration as an industry standard qualification test for creep corrosion. This paper will address the important question of how relative humidity affects creep corrosion. A creep corrosion tendency that is inversely proportional to relative humidity may allow data center administrators to eliminate creep corrosion simply by controlling the relative humidity in the data center,thus, avoiding the high cost of gas-phase filtration of gaseous contamination. The creep corrosion relative humidity dependence will be studied using a modified version of the iNEMI FOS test chamber. The design modification allows the achievement of relative humidity as low as 15% in the presence of the chlorine-releasing bleach aqueous solution. The paper will report on the dependence of creep corrosion on humidity in the 15 to 80% relative humidity range by testing ENIG (gold on electroless nickel), ImAg (immersion silver) and OSP (organic surface preservative) finished PCBs, soldered with organic acid flux.
Technical Library | 2020-08-27 01:22:45.0
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.
Technical Library | 2013-02-07 17:01:46.0
Silicone contamination is known to have a negative impact on assembly processes such as soldering, adhesive bonding, coating, and wire bonding. In particular, silicone is known to cause de-wetting of materials from surfaces and can result in adhesive failures. There are many sources for silicone contamination with common sources being mold releases or lubricants on manufacturing tools, offgassing during cure of silicone paste adhesives, and residue from pressure sensitive tape. This effort addresses silicone contamination by quantifying adhesive effects under known silicone contaminations. The first step in this effort identified an FT-IR spectroscopic detection limit for surface silicone utilizing the area under the 1263 cm-1 (Si-CH3) absorbance peak as a function of concentration (µg/cm2). The next step was to pre-contaminate surfaces with known concentrations of silicone oil and assess the effects on surface wetting and adhesion. This information will be used to establish guidelines for silicone contamination in different manufacturing areas within Harris Corporation... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2012-08-02 21:05:14.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. Pure tin is a common finish for copper hook up wire, coaxial cable, ground braid and harness assemblies used on electronic assemblies. Historically there have been fewer reports o
Technical Library | 2010-08-05 18:39:39.0
Variability analysis is important in successfully deploying multi-gigabit backplane printed wiring boards (PWBs) with growing numbers of high-speed SerDes links. We discuss the need for large sample sizes to obtain accurate variability estimates of SI me
Technical Library | 2017-09-07 13:56:11.0
As a surface finish for PCBs, Electroless Nickel/Electroless Palladium/Immersion Gold (ENEPIG) was selected over Electroless Nickel/Immersion Gold (ENIG) for CMOS image sensor applications with both surface mount technology (SMT) and gold ball bonding processes in mind based on the research available on-line. Challenges in the wire bonding process on ENEPIG with regards to bondability and other plating related issues are summarized.
Technical Library | 2023-08-04 15:27:30.0
A designed experiment evaluated the influence of several variables on appearance and strength of Pb-free solder joints. Components, with leads finished with nickel-palladium-gold (NiPdAu), were used from Texas Instruments (TI) and two other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electrolysis Ni/immersion Au), reflow atmosphere, reflow temperature, Pd thickness in the NiPdAu finish, and thermal aging. Height of solder wetting to component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a "lead pull" test determined the maximum force needed to pull the component lead from the PWB. This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have the greatest contribution to the height of lead side wetting. Reflow temperature, palladium thickness, and preconditioning had very little impact on side-wetting height. For lead pull, variance in the data was relatively small and the factors tested had little impact.
Technical Library | 2024-04-08 15:46:36.0
A designed experiment evaluated the influence of several variables on appearance and strength of Pb-free solder joints. Components, with leads finished with nickel-palladium-gold (NiPdAu), were used from Texas Instruments (TI) and two other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electrolysis Ni/immersion Au), reflow atmosphere, reflow temperature, Pd thickness in the NiPdAu finish, and thermal aging. Height of solder wetting to component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a "lead pull" test determined the maximum force needed to pull the component lead from the PWB. This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have the greatest contribution to the height of lead side wetting. Reflow temperature, palladium thickness, and preconditioning had very little impact on side-wetting height. For lead pull, variance in the data was relatively small and the factors tested had little impact.
Technical Library | 2012-10-11 19:50:09.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper shows the benefits by using a pure palladium Layer in the ENEPIG (Electroless Nickel, Electroless Palladium, Immersion Gold) and ENEP (Electroless Nickel, Electroless P
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