Technical Library | 2016-03-03 17:25:26.0
This paper discusses a nano copper based paste for use in via filling. The company manufactures nano copper and disperses the coated nano copper into a paste in combination with micron copper. The resultant paste is injected or fills a via. The via is subsequently sintered by means of photonic sintering, or by heat in a reducing environment. The process will be accomplished in under an hour and results in filled solid copper vias.
Technical Library | 2013-03-28 16:18:22.0
For the last couple of years, the main concerns regarding the electrical performance of blank PCB boards were impedance and ohmic resistance. Just recently, the need to reduce insertion loss came up in discussions with blank board customers (...) The paper describes the test vehicle and the testing methodology and discusses in detail the electrical performance characteristics. The influence of the independent variables on the performance characteristics is presented. Finally the thermal reliability of the boards built applying different copper foils and oxide replacements was investigated.
Technical Library | 2018-05-23 12:12:43.0
Driven by miniaturization, cost reduction and tighter requirements for electrical and thermal performance, the use of lead-frame based bottom-termination components (LF-BTC) as small-outline no-leads (SON), quad-flat no leads (QFN) packages etc., is increasing. However, a major distractor for the use of such packages in high-reliability applications has been the lack of a visible solder (toe) fillet on the edge surface of the pins: because the post-package assembly singulation process typically leaves bare copper leadframe at the singulation edge, which is not protected against oxidation and thus does not easily solder-wet, a solder fillet (toe fillet) does not generally develop.
Technical Library | 2014-07-24 16:26:34.0
Wire bonding a die to a package has traditionally been performed using either aluminum or gold wire. Gold wire provides the ability to use a ball and stitch process. This technique provides more control over loop height and bond placement. The drawback has been the increasing cost of the gold wire. Lower cost Al wire has been used for wedge-wedge bonds but these are not as versatile for complex package assembly. The use of copper wire for ball-stitch bonding has been proposed and recently implemented in high volume to solve the cost issues with gold. As one would expect, bonding with copper is not as forgiving as with gold mainly due to oxide growth and hardness differences. This paper will examine the common failure mechanisms that one might experience when implementing this new technology.
Technical Library | 2020-03-12 13:10:35.0
The electronics industry is further progressing in terms of smaller, faster, smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades. (...) This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes, microvias and other copper plated structures on PCBs.
Technical Library | 2014-03-06 19:04:07.0
Over the last few years, there has been an increase in the rate of Head-in-Pillow component soldering defects which interrupts the merger of the BGA/CSP component solder spheres with the molten solder paste during reflow. The issue has occurred across a broad segment of industries including consumer, telecom and military. There are many reasons for this issue such as warpage issues of the component or board, ball co-planarity issues for BGA/CSP components and non-wetting of the component based on contamination or excessive oxidation of the component coating. The issue has been found to occur not only on lead-free soldered assemblies where the increased soldering temperatures may give rise to increase component/board warpage but also on tin-lead soldered assemblies.
Technical Library | 2021-11-03 16:52:47.0
This paper proposes the integration of pulsed photonic sintering into multi-material additive manufacturing processes in order to produce multifunctional components that would be nearly impossible to produce any other way. Pulsed photonic curing uses high power Xenon flash lamps to thermally fuse printed nanomaterials such as conductive metal inks. To determine the feasibility of the proposed integration, three different polymer additive manufacturing materials were exposed to typical flash curing conditions using a Novacentrix Pulseforge 3300 system. FTIR analysis revealed virtually no change in the polymer substrates, thus indicating that the curing energy did not damage the polymer. Next, copper traces were printed on the same substrate, dried, and photonically cured to establish the feasibility of thermally fusing copper metal on the polymer additive manufacturing substrates. Although drying defects were observed, electrical resistivity values ranging from 0.081 to 0.103 Ω/sq. indicated that high temperature and easily oxidized metals can be successfully printed and cured on several commonly used polymer additive manufacturing materials. These results indicate that pulsed photonic curing holds tremendous promise as an enabling technology for next generation multimaterial additive manufacturing processes.
Technical Library | 2009-01-15 00:42:58.0
Tin-silver-copper has received much publicity in recent years as the lead-free solder of choice. SAC305 was endorsed by the IPC Solder Value Product Council in the United States as the preferred option for SMT assembly; most assemblers have transitioned to this alloy for their solder paste requirements. The SAC305 alloy due to its 3.0% content of silver is expensive when compared to traditional 63/37 for this reason many wave assemblers are opting for less costly options such as tin-copper based solders for their wave, selective and dip tinning operations.
Technical Library | 2013-02-08 22:56:47.0
Solder voiding is present in the majority solder joints and is generally accepted when the voids are small and the total void content is minimal. X-ray methods are the predominate method for solder void analysis but this method can be quite subjective for non grid array components due to the two dimensional aspects of X-ray images and software limitations. A novel method of making a copper "sandwich" to simulate under lead and under component environs during reflow has been developed and is discussed in detail. This method has enabled quantitative solder paste void analysis for lead free and specialty paste development and process refinement. Profile and paste storage effects on voiding are discussed. Additionally an optimal design and material selection from a solder void standpoint for a heat spreader on a BCC (Bumpered Chip Carrier) has been developed and is discussed.
Technical Library | 2013-12-27 10:39:21.0
The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.
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