Technical Library | 2015-12-31 15:19:28.0
Today's consumer electronic product are characterized by miniatuization, portability and light weight with high performance, especially for 3G mobile products. In the future more fine pitch CSPs (0.4mm) component will be required. However, the product reliability has been a big challenge with the fine pitch CSP. Firstly, the fine pitch CSPs are with smaller solder balls of 0.25mm diameter or even smaller. The small solder ball and pad size do weaken the solder connection and the adhesion of the pad and substrate, thus the pad will peel off easily from the PCB substrate. In addition, miniature solder joint reduce the strength during mechanical vibration, thermal shock, fatigue failure, etc. Secondly, applying sufficient solder paste evenly on the small pad of the CSP is difficult because stencil opening is only 0.25mm or less. This issue can be solved using the high end type of stencil such as Electroforming which will increase the cost.
Technical Library | 2021-01-03 19:24:52.0
Reflow soldering is the primary method for interconnecting surface mount technology (SMT) applications. Successful implementation of this process depends on whether a low defect rate can be achieved. In general, defects often can be attributed to causes rooted in all three aspects, including materials, processes, and designs. Troubleshooting of reflow soldering requires identification and elimination of root causes. Where correcting these causes may be beyond the reach of manufacturers, further optimizing the other relevant factors becomes the next best option in order to minimize the defect rate.
Technical Library | 2015-03-12 18:26:16.0
Miniaturization and the integration of a growing number of functions in portable electronic devices require an extremely high packaging density for the active and passive components. There are many ways to increase the packaging density and a few examples would be to stack them with Package on Package (PoP), fine pitch CSP's, 01005 and last but not least reduced component to component spacing for active and passive components (...)This paper will discuss different layouts, assembly and material selections to reduce component to component spacing down to 100-125um (4-5mil) from today’s mainstream of 150-200um (6-8mil) component to component spacing.
Technical Library | 2021-09-08 14:03:55.0
There is need in the industry to understand the effects of silver presence in solders from various applications perspective. This article will attempt to present a review of the key published results on the silver containing alloys along with results of our internal studies on wave soldering, surface mount and BGA/CSP applications. Advantages and disadvantages of silver at different levels will be discussed. Specifically this report will focus on the effect of silver on process conditions, drop shock resistance, solder joint survivability in high strain rate situations, thermal fatigue resistance, Cu dissolution and effects of silver in combination with other alloy additives. Specific application problems demanding high silver level and other requiring silver level to the minimum will be discussed.
Technical Library | 2015-01-05 17:38:26.0
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products. This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC-9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Technical Library | 2023-09-26 19:14:44.0
The transition from tin-lead to lead free soldering in the electronics manufacturing industry has been in progress for the past 10 years. In the interim period before lead free assemblies are uniformly accepted, mixed formulation solder joints are becoming commonplace in electronic assemblies. For example, area array components (BGA/CSP) are frequently available only with lead free Sn-Ag-Cu (SAC) solder balls. Such parts are often assembled to printed circuit boards using traditional 63Sn-37Pb solder paste. The resulting solder joints contain unusual quaternary alloys of Sn, Ag, Cu, and Pb. In addition, the alloy composition can vary across the solder joint based on the paste to ball solder volumes and the reflow profile utilized. The mechanical and physical properties of such Sn-Ag-Cu-Pb alloys have not been explored extensively in the literature. In addition, the reliability of mixed formulation solder joints is poorly understood.
Technical Library | 2023-07-25 16:42:54.0
Printing solder paste for very small components like .3mm pitch CSP's and 01005 Chip Components is a challenge for the printing process when other larger components like RF shields, SMT Connectors, and large chip or resistor components are also present on the PCB. The smaller components require a stencil thickness typically of 3 mils (75u) to keep the Area Ratio greater than .55 for good paste transfer efficiency. The larger components require either more solder paste height or volume, thus a stencil thickness in the range of 4 to 5 mils (100 to 125u). This paper will explore two stencil solutions to solve this dilemma. The first is a "Two Print Stencil" option where the small component apertures are printed with a thin stencil and the larger components with a thicker stencil with relief pockets for the first print. Successful prints with Keep-Outs as small as 15 mils (400u) will be demonstrated. The second solution is a stencil technology that will provide good paste transfer efficiency for Area Ratio's below .5. In this case a thicker stencil can be utilized to print all components. Paste transfer results for several different stencil types including Laser-Cut Fine Grain stainless steel, Laser-Cut stainless steel with and w/o PTFE Teflon coating, AMTX E-FAB with and w/o PTFE coating for Area Ratios ranging from .4 up to .69.
Technical Library | 2023-01-10 20:15:42.0
Over the past years there has been consistent growth in the use of electroless nickel / immersion gold (ENIG) as a final finish. The finish is now frequently being used for PBGA, CSP, QFP and COB and more recently gathered considerable interest as a low cost under-bump metallization for flip chip bumping application. One of the largest users for this finish has been the telecommunication industry, were millions of square meters of PCBs with ENIG have been successfully used. The nickel layer offers advantages such as multiple soldering cycles and hand reworks without copper dissolution being a factor. The nickel also acts as a reinforcement to improve through-hole and blind micro via thermal integrity. In addition the nickel layer offers advantages such as co-planarity, Al-wire bondability and the use as contact surface for keypads or contact switching. Especially those pads, which are not covered by solder need a protective coating in corrosive environment – such as high humidity or pollutant gas.
Technical Library | 2013-12-27 10:39:21.0
The head-in-pillow defect has become a relatively common failure mode in the industry since the implementation of Pb-free technologies, generating much concern. A head-in-pillow defect is the incomplete wetting of the entire solder joint of a Ball-Grid Array (BGA), Chip-Scale Package (CSP), or even a Package-On-Package (PoP) and is characterized as a process anomaly, where the solder paste and BGA ball both reflow but do not coalesce. When looking at a cross-section, it actually looks like a head has pressed into a soft pillow. There are two main sources of head-in-pillow defects: poor wetting and PWB or package warpage. Poor wetting can result from a variety of sources, such as solder ball oxidation, an inappropriate thermal reflow profile or poor fluxing action. This paper addresses the three sources or contributing issues (supply, process & material) of the head-in-pillow defects. It will thoroughly review these three issues and how they relate to result in head-in pillow defects. In addition, a head-in-pillow elimination plan will be presented with real life examples will be to illustrate these head-in-pillow solutions.
Technical Library | 2023-11-20 18:49:11.0
Non-destructive testing during the manufacture of printed wiring boards (PWBs) has become ever more important for checking product quality without compromising productivity. Using x-ray inspection, not only provides a non-destructive test but also allows investigation within optically hidden areas, such as the quality of post solder reflow of area array devices (e.g. BGAs, CSPs and flip chips). As the size of components continues to diminish, today's x-ray inspection systems must provide increased magnification, as well as better quality x-ray images to provide the necessary analytical information. This has led to a number of x-ray manufacturers offering digital x-ray inspection systems, either as standard or as an option, to satisfy these needs. This paper will review the capabilities that these digital x-ray systems offer compared to their analogue counterparts. There is also a discussion of the various types of digital x-ray systems that are available and how the use of different digital detectors influences the operational capabilities that such systems provide.
