Technical Library | 2019-06-20 00:09:49.0
It is well known that during service the layer of Cu6Sn5 intermetallic at the interface between the solder and a Cu substrate grows but the usual concern has been that if this layer gets too thick it will be the brittleness of this intermetallic that will compromise the reliability of the joint, particularly in impact loading. There is another level of concern when the Cu-rich Cu3Sn phase starts to develop at the Cu6Sn5/Cu interface and an imbalance in the diffusion of atomic species, Sn and Cu, across that interface results in the formation at the Cu3Sn/Cu interface of Kirkendall voids, which can also compromise reliability in impact loading. However, when, as is the case in some microelectronics, the copper substrate is thin in relation to the volume of solder in the joint an overriding concern is that all of the Cu will be consumed by reaction with Sn to form these intermetallics.This paper reports an investigation into the kinetics of the growth of the interfacial intermetallic, and the consequent reduction in the thickness of the Cu substrate in solder joints made with three alloys, Sn-3.0Ag-0.5Cu, Sn-0.7Cu-0.05Ni and Sn-1.5Bi-0.7Cu-0.05Ni.
Technical Library | 2015-06-22 16:39:47.0
Surface finishing is an integral part of any PCB fabrication. It is generally applied to exposed Cu connectors and conductors on the board. Surface finishing has numerous important functions. It serves as a protective layer for the Cu connectors during storage. The surface finish helps minimize or reduce tarnish of the Cu substrate. Additionally, since it is the layer that comes into contact with other components during assembly, it ensures good solderability between the PCB and the component during assembly. Furthermore after assembly, the finish helps prolong the integrity of the solder joint during use. A general review of common PCB surface finishes is presented. The advantages and disadvantages of each are discussed and compared.
Technical Library | 2024-06-19 13:59:50.0
The solderability of a nickel-palladium-gold (Ni-Pd-Au) finish on a Cu substrate was evaluated for the Pb-free solder, 95.5Sn-3.9Ag-0.6 Cu (wt.%, abbreviated Sn-Ag-Cu) and the eutectic 63Sn-37 Pb (Sn-Pb) alloy. The solder temperature was 245ºC. The flux was a rosin-based mildly activated (RMA) solution. The Ni-Pd-Au finish was tested in the as-fabricated condition as well as after exposure to one of the following accelerated storage (shelf life) regiments:
Technical Library | 2022-03-02 21:26:51.0
The solderability of a nickel-palladium-gold (Ni-Pd-Au) finish on a Cu substrate was evaluated for the Pb-free solder, 95.5Sn-3.9Ag-0.6 Cu (wt.%, abbreviated Sn-Ag-Cu) and the eutectic 63Sn-37 Pb (Sn-Pb) alloy. The solder temperature was 245ºC. The flux was a rosin-based mildly activated (RMA) solution. The Ni-Pd-Au finish was tested in the as-fabricated condition as well as after exposure to one of the following accelerated storage (shelf life) regiments: (1) 33.6, 67.2, or 336 hours in the Battelle Class 2 flowing gas environment or (2) 5, 16, or 24 hours of steam aging (88ºC, 90%RH).
Technical Library | 2021-10-20 18:21:06.0
The solderability of the SAC305 alloy in contact with printed circuit boards (PCB) having different surface finishes was examined using the wetting balance method. The study was performed at a temperature of 260 _C on three types of PCBs covered with (1) hot air solder leveling (HASL LF), (2) electroless nickel immersion gold (ENIG), and (3) organic surface protectant (OSP), organic finish, all on Cu substrates and two types of fluxes (EF2202 and RF800). The results showed that the PCB substrate surface finish has a strong effect on the value of both the wetting time t0 and the contact angle h. The shortest wetting time was noted for the OSP finish (t0 = 0.6 s with EF2202 flux and t0 = 0.98 s with RF800 flux), while the ENIG finish showed the longest wetting time (t0 = 1.36 s with EF2202 flux and t0 = 1.55 s with RF800 flux). The h values calculated from the wetting balance tests were as follows: the lowest h of 45_ was formed on HASL LF (EF2202 flux), the highest h of 63_ was noted on the OSP finish, while on the ENIG finish, it was 58_ (EF2202 flux). After the solderability tests, the interface characterization of cross-sectional samples was performed by means of scanning electron microscopy coupled with energy dispersive spectroscopy.
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
Technical Library | 2021-11-03 17:05:39.0
Additively printed circuits provide advantages in reduced waste, rapid prototyping, and versatile flexible substrate choices relative to conventional circuit printing. Copper (Cu) based inks along with intense pulsed light (IPL) sintering can be used in additive circuit printing. However, IPL sintered Cu typically suffer from poor solderability due to high roughness and porosity. To address this, hybrid Cu ink which consists of Cu precursor/nanoparticle was formulated to seed Cu species and fill voids in the sintered structure. Nickel (Ni) electroplating was utilized to further improve surface solderability. Simulations were performed at various electroplating conditions and Cu cathode surface roughness using the multi-physics finite element method. By utilizing a mask during IPL sintering, conductivity was induced in exposed regions; this was utilized to achieve selective Ni-electroplating. Surface morphology and cross section analysis of the electrodes were observed through scanning electron microscopy and a 3D optical profilometer. Energy dispersive X-ray spectroscopy analysis was conducted to investigate changes in surface compositions. ASTM D3359 adhesion testing was performed to examine the adhesion between the electrode and substrate. Solder-electrode shear tests were investigated with a tensile tester to observe the shear strength between solder and electrodes. By utilizing Cu precursors and novel multifaceted approach of IPL sintering, a robust and solderable Ni electroplated conductive Cu printed electrode was achieved.
Technical Library | 2010-07-08 19:49:59.0
Aging characteristics of new lead free solder alloys are in question by many experts because of higher amount of tin’s effect on the diffusion of other metals, primarily copper, to create undesirable boundary intermetallics over long periods of time and even moderately elevated temperatures. A primary layer of intermetallics, Cu6Sn5 forms as the liquid solder makes contact with the solid copper substrate. This reaction however ceases as the solder temperature falls below that of liquidus. A secondary intermetallic Cu3Sn1, an undesirable weak and brittle layer, is thought to form over time and may be accelerated by even mildly elevated temperatures in electronic modules such as laptops under power. This project was designed to quantify the growth rate of Cu3Sn1 over an extended period of time in a thermal environment similar to a laptop in the power on mode.
Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
Technical Library | 2013-01-24 19:16:35.0
The electronics industry has mainly adopted the higher melting point Sn3Ag0.5Cu solder alloys for lead-free reflow soldering applications. For applications where temperature sensitive components and boards are used this has created a need to develop low melting point lead-free alloy solder pastes. Tin-bismuth and tin-bismuth-silver containing alloys were used to address the temperature issue with development done on Sn58Bi, Sn57.6Bi0.4Ag, Sn57Bi1Ag lead-free solder alloy pastes. Investigations included paste printing studies, reflow and wetting analysis on different substrates and board surface finishes and head-in-pillow paste performance in addition to paste-in-hole reflow tests. Voiding was also investigated on tin-bismuth and tin-bismuth-silver versus Sn3Ag0.5Cu soldered QFN/MLF/BTC components. Mechanical bond strength testing was also done comparing Sn58Bi, Sn37Pb and Sn3Ag0.5Cu soldered components. The results of the work are reported.
