Technical Library | 2012-10-25 16:34:02.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper will examine stencil technologies (including Laser and Electroform), Aperture Wall coatings (including Nickel-Teflon coatings and Nano-coatings), and how these parameters influence paste transfer for miniature devices with Area Ratios less than the standard recommended lower limit of .5. A matrix of print tests will be utilized to compare paste transfer and measure the effectiveness of the different stencil configurations. Area Ratios ranging from .32 to .68 will be investigated.
Technical Library | 2012-11-08 19:16:39.0
first published in the 2012 IPC APEX EXPO technical conference proceedings. Twenty-nine different cells phones have been disassembled, ground up, dissolved and analyzed for elemental content, mainly for information about the metals present in the phones, but also for some metalloids and non-metals. The paper will discuss the method used and propose possible sources in the telephones for certain elements of interest and the reasons for the interest in some of the elements.
Technical Library | 2013-01-31 18:43:15.0
There are three key industry trends that are driving the need for temperature-dependent warpage measurement: the trend toward finer-pitch devices, the emergence of lead-free processing, and changes in device form factors. Warpage measurement has become a key measurement for analysis; prevention and prediction of interconnect defects and has been employed in failure analysis labs and production sites worldwide. First published in the 2012 IPC APEX EXPO technical conference proceedings
Technical Library | 2013-03-21 21:24:49.0
This paper explores the behaviour of a copper test vehicle with multiple reflowed solder joints, which has direct relevance to ball grid arrays (BGA) and high density interconnect structures. The paper explores the relative stress conditions on the distributed joints and the sensitivity to ball joint shape... First published in the 2012 IPC APEX EXPO technical conference proceedings
Technical Library | 2013-04-11 15:43:17.0
With the explosion of growth in handheld electronics devices, manufacturers have been forced to look for ways to reinforce their assemblies against the inevitable bumps and drops that their products experience in the field. One method of reinforcement has been the utilization of underfills to "glue" certain SMDs to the PCB. Bumped SMDs attached to the PCB with a no-clean soldering process offer the unavoidable scenario of the underfill coming in contact with a flux residue. This may or may not create a reliability issue... First published in the 2012 IPC APEX EXPO technical conference proceedings
Technical Library | 2013-04-25 11:42:01.0
Specification and control of surface roughness of copper conductors within printed circuit boards (PCBs) are increasingly desirable in multi-GHz designs as a part of signal-integrity failure analysis on high-speed PCBs. The development of a quality-assurance method to verify the use of foils with specified roughness grade during the PCB manufacturing process is also important... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2013-05-09 14:35:18.0
Atmospheric dust consists of solids suspended in air. Dust is well known for its complex nature. It normally includes inorganic mineral materials, water soluble salts, organic materials, and a small amount of water. The impact of dust on the reliability of printed circuit board assemblies (PCBAs) is ever-growing, driven by the miniaturization of technology and the increasing un-controlled operating conditions with more dust exposure in telecom and information industries... First published in the 2012 IPC APEX EXPO technical conference proceedings.
Technical Library | 2013-06-27 14:00:27.0
While IC level ESD design and the necessary protection levels are well understood, system ESD protection strategy and design efficiency have only been dealt with in an ad hoc manner. This is most obvious when we realize that a consolidated approach to system level ESD design between system manufacturers and chip suppliers has been rare. This White Paper discusses these issues in the open for the first time, and offers new and relevant insight for the development of efficient system level ESD design.
Technical Library | 2014-04-24 16:37:42.0
By May 31, 2014, it is expected that companies, officially known as issuers, will be required to take the unprecedented step of submitting their first conflict minerals disclosures to the Securities and Exchange Commission, or SEC. This paper is intended to describe the content that certain sustainable and responsible investors, or SRIs, and nongovernmental organizations, or NGOs, expect to see in an issuer's Specialized Disclosure, or Form SD, and Conflict Minerals Report, or CMR, if a CMR is deemed necessary.
Technical Library | 2016-04-28 14:43:23.0
Underfilling is a long-standing process issued from the micro-electronics that can enhance the robustness and the reliability of first or second-level interconnects for a variety of electronic applications. Its usage is currently spreading across the industry fueled by the decreasing reliability margins induced by the miniaturization and interconnect pitch reduction. (...) This paper will address the control of surface mount under filled assemblies, focusing on applicable inspection techniques and possible options to overcome their limitations.
