Technical Library | 1999-08-27 09:29:49.0
Contract packaging houses have to contend with a large mix of die types and products. Flexibility and quick turnaround of package types is a must in this industry. Traditional methods of die encapsulation, (i.e., use of transfer-molding techniques), are only cost effective when producing a large number of components. Liquid encapsulants now provide similar levels of reliability1, and are cost effective...
Technical Library | 2023-09-18 03:53:42.0
好的，以下是根据标题"LED Lens Production Line Solution"写的SEO元描述和标题： SEO Meta Description (300 characters) LED Lens Production Line Solutions: The Complete Package for Efficient and Reliable LED Lens Manufacturing Our LED lens production line solutions are the perfect way to improve your LED lens manufacturing efficiency and reliability. Our solutions include all the equipment and services you need to produce high-quality LED lenses, from lens molding to assembly.
Technical Library | 2015-09-23 22:08:32.0
A molded interconnect device (MID) is an injection molded thermoplastic substrate which incorporates a conductive circuit pattern and integrates both mechanical and electrical functions. (...) Flip chip bonding of bare die on MID can be employed to fully utilize MID’s advantage in device miniaturization. Compared to the traditional soldering process, thermo-compression bonding with gold stud bumps provides a clear advantage in its fine pitch capability. However, challenges also exist. Few studies have been made on thermocompression bonding on MID substrate, accordingly little information is available on process optimization, material compatibility and bonding reliability. Unlike solder reflow, there is no solder involved and no “self-alignment,” therefore the thermo-compression bonding process is significantly more dependent on the capability of the machine for chip assembly alignment.
Technical Library | 2010-11-18 19:19:50.0
In this article we present both a relatively new and innovative family of packages that is suitable for medium pin count needs and an innovative method for fabricating the substrates for such a package. With respect to lead count, this packaging family is
Technical Library | 2020-09-16 21:24:56.0
Additive manufacturing processes typically used for mechanical parts can be combined with enhanced technologies for electronics production to enable a highly flexible manufacturing of personalized 3D electronic devices. To illustrate different approaches for implementing electrical and electronic functionality, conductive paths and electronic components were embedded in a powder bed printed substrate using an enhanced 3D printer. In addition, a modified Aerosol Jet printing process and assembly technologies adapted from the technology of Molded Interconnect Devices were applied to print circuit patterns and to electrically interconnect components on the surface of the 3D substrates.
Institute for Factory Automation and Production Systems (FAPS)
Technical Library | 2018-10-18 15:41:45.0
One specific market space of interest to emerging printed electronics is In Mold Label (IML) technology. IML is used in many consumer products and white good applications. When combined with electronics, the In Mold Electronics (IME) adds compelling new product functionality. Many of these products have multi-dimensional features and therefore require thermoforming processes in order to prepare the labels before they are in-molded. While thermoforming is not a novel technique for IML, the addition of printed electronic functional traces is not well documented. There is little or no published work on printed circuit performance and design interactions in the thermoforming process that could inform improved IME product designs. A general full factorial Design of Experiments (DOE) was used to analyze the electrical performance of the conductive silver ink trace/polycarbonate substrate system. Variables of interest include trace width, height of draw, and radii of both top and bottom curvatures in the draw area. Thermoforming tooling inserts were fabricated for eight treatment combinations of these variables. Each sample has one control and two formed strips. Electrical measurements were taken of the printed traces on the polymer sheets pre- and post- forming with a custom fixture to evaluate the effect on resistance. The design parameters found to be significant were draw height and bottom radius, with increased draw and smaller bottom curvature radii both contributing to the circuits’ resistance degradation. Over the ranges evaluated, the top curvature radii had no effect on circuit resistance. Interactions were present, demonstrating that circuit and thermoforming design parameters need to be studied as a system. While significant insight impacting product development was captured further work will be executed to evaluate different ink and substrate material sets, process variables, and their role in IME.
Technical Library | 2014-06-02 11:03:45.0
With the advancement of the electronic industry, package on package (POP) has become increasingly popular IC package for electronic devices, particularly POP TMV (Through Mold Vials) in mobile devices due to its benefits of miniaturization, design flexibility and cost efficiency. However, there are some issues that have been reported such as SIR drop due to small gap between top and bottom components, difficulty underfilling and rework due to stacked IC components and process yield issues. Some suppliers have reported using some methods such as dipping epoxy paste or epoxy flux to address these issues, but so far no customer has reported using these methods or materials in their mass production. In order to address these issues for POP TMV assembly, YINCAE has successfully developed and commercialized the first individual solder joint encapsulant adhesive for mass production for years.
Technical Library | 2015-01-22 17:32:27.0
Temperature requirements for ceramic capacitors have increased significantly with recent advances in deep-well drilling technology. Increasing demand for oil and natural gas has driven the technology to deeper and deeper deposits resulting in extreme temperature environments up to 200°C and above. A novel capacitor solution utilizing temperature-stable base-metal electrode capacitors in a molded and leaded package addresses the growing market high temperature demands of (1) capacitance stability, (2) long service life, and (3) mechanical durability. A range of high temperature C0G capacitors capable of meeting this 200°C and above high temperature environment has been developed. This paper will review the electrical, reliability, and mechanical performance of this new capacitor solution
Technical Library | 2017-07-06 15:50:17.0
Head-in-pillow (HiP) is a BGA defect which happens when solder balls and paste can't contact well during reflow soldering. Package warpage was one of the major reasons for HiP formation. In this paper, package warpage was measured and simulated. It was found that the package warpage was sensitive to the thickness of inside chips. A FEM method considering viscoelastic property of mold compound was introduced to simulate package warpage. The CTE mismatch was found contributes to more than 90% of the package warpage value when reflowing at the peak temperature. A method was introduced to measure the warpage threshold, which is the smallest warpage value that may lead to HiP. The results in different atmospheres showed that the warpage threshold was 50μm larger in N2 than that in air, suggesting that under N2 atmosphere the process window for HiP defects was larger than that under air, which agreed with the experiments.
Technical Library | 2015-01-28 17:39:34.0
Stacking heterogeneous semiconductor die (memory and logic) within the same package outline can be considered for less complex applications but combining the memory and processor functions in a single package has compromised test efficiency and overall package assembly yield. Separation and packaging the semiconductor functions into sections, on the other hand, has proved to be more efficient and, even though two interposers are required, more economical. The separated logic and memory sections are configured with the same uniform outline for vertical stacking (package-on-package). The most common configuration places the logic section as the base with second tier memory section soldered to a mating contact pattern. This paper addresses the primary technological challenges for reducing contact pitch and package-on-package interface technology.
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