Technical Library | 2008-10-29 18:45:53.0
Growing demand for compact, multi-function electronics products has accelerated component miniaturization and high-density placement, creating new challenges for the electronics manufacturing industry. It is no longer adequate to simply place parts accurately per a pre-defined CAD assembly program because solder paste alignment errors are increasing for numerous reasons. The solution to this problem is a system in which the placement machine can automatically detect and compensate for misalignment of the solder paste to produce high-quality boards regardless of the process errors beforehand.
Technical Library | 2017-09-25 10:36:52.0
Laser wire stripping was developed by NASA in the 1970s as part of the Space Shuttle program. The technology made it possible to use smaller sized wires with thinner insulations, without risk of the damage that can be caused by traditional mechanical wire stripping methods. Laser wire stripping technology was commercialized in the 1990s and was initially used for aerospace and defense applications. Laser wire stripping then grew significantly when the consumer electronics market exploded as lasers became the only stripping solution for the tiny data cables found in laptops, mobile phones and other consumer electronics products. Another large industry that has adopted laser wire stripping methods, and for good reason, is high-end medical device manufacturing.
Technical Library | 2023-11-20 18:18:34.0
When x-ray inspection is used as part of a quality assurance program for any assembled device, steps must be taken early in the design stage to anticipate the use of x-ray inspection later in the development and production processes. This is a lesson that electronic assembly manufacturers learned years ago, and that medical device manufacturers are also discovering. There are several steps involved in learning how to interpret x-ray images, and how to design for x-ray inspection. First, manufacturers need to understand the nature of the x-ray shadow and its modalities; then they need to see how medical device developers and manufacturers are using x-ray inspection; finally, they need to consider taking measures early in the design process to ensure a clear, accurate image when the assembled device undergoes x-ray inspection.
Technical Library | 2018-10-29 05:03:59.0
We found that NPI process of SMT is mostly similar and sometimes overlapping to tooling process. In addition, in most cases the programmer is part of the team working on the NPI process. So, QPlan was extended with NPI Tools as a part of tooling process. This allows the team to carry out the NPI process at offline. And at the end of it, they can create corrected SMT program at zero time.
Technical Library | 2021-12-03 01:22:50.0
CNC machines is the abbreviation of "Computer Numerical Control" machines. It is an automatic machine tool with program control system. The control system can logically process the programs with control codes or other symbolic instructions, decode them and express them with coded numbers. Next, the coded numbers will be input into the numerical control device through the information carrier. After calculation and processing, the numerical control device sends out various control signals to control the action of the machine tool. CNC machine can automatically produce parts or other products according to the shape and size specified by the drawings.
Technical Library | 2021-09-08 14:10:12.0
The Pb-Free Alloy Characterization Program sponsored by International Electronics Manufacturing Initiative (iNEMI) is conducting an extensive investigation using accelerated temperature cycling (ATC) to evaluate ball grid array (BGA) thermal fatigue performance of 12 commercial or developmental Sn based Pb-free solder alloys. This paper presents the initial findings from a specific subset of the temperature cycling test matrix. The focus is on comparing alloy performance for two of the most commonly specified temperature cycles, 0 to 100 °C and -40 to 125 °C.
Technical Library | 2014-09-04 17:43:19.0
The counterfeiting of electronic components has become a major challenge in the 21st century. The electronic component supply chain has been greatly affected by widespread counterfeit incidents. A specialized service of testing, detection, and avoidance must be created to tackle the worldwide outbreak of counterfeit integrated circuits (ICs). So far, there are standards and programs in place for outlining the testing, documenting, and reporting procedures. However, there is not yet enough research addressing the detection and avoidance of such counterfeit parts. In this paper we will present, in detail, all types of counterfeits, the defects present in them, and their detection methods. We will then describe the challenges to implementing these test methods and to their effectiveness. We will present several anti-counterfeit measures to prevent this widespread counterfeiting, and we also consider the effectiveness and limitations of these anti-counterfeiting techniques.
Technical Library | 2020-10-08 01:01:01.0
Flexible hybrid electronics (FHE) is emerging as a promising solution to combine the benefits of printed electronics and silicon technology. FHE has many high-impact potential areas, such as wearable applications, health monitoring, and soft robotics, due to its physical advantages, which include light weight, low cost and the ability conform to different shapes. However, physical deformations in the field can lead to significant testing and validation challenges. For example, designers must ensure that FHE devices continue to meet their specs even when the components experience stress due to bending. Hence, physical deformation, which is hard to emulate, has to be part of the test procedures for FHE devices. This paper is the first to analyze stress experience at different parts of FHE devices under different bending conditions. We develop a novel methodology to maximize the test coverage with minimum number of text vectors with the help of a mixed integer linear programming formulation. We validate the proposed approach using an FHE prototype and COMSOL Multiphysics simulations
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
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