Technical Library: scott (Page 1 of 2)

Determination of Copper Foil Surface Roughness from Micro-section Photographs

Technical Library | 2013-04-25 11:42:01.0

Specification and control of surface roughness of copper conductors within printed circuit boards (PCBs) are increasingly desirable in multi-GHz designs as a part of signal-integrity failure analysis on high-speed PCBs. The development of a quality-assurance method to verify the use of foils with specified roughness grade during the PCB manufacturing process is also important... First published in the 2012 IPC APEX EXPO technical conference proceedings.

Cisco Systems, Inc.

Effect of BGA Reballing and its Influence on Ball Shear Strength

Technical Library | 2013-07-11 15:22:40.0

This research paper will focus on the effect of various parameters that are used to reball a BGA and their effect on the overall shear strength. Factors that will be looked at include the type of BGA (SAC305 or 63Sn/37Pb), the alloy used to reball (SAC405 or 63Sn/37Pb), the type of flux used (Water Soluble or No Clean), and the environment in which reballing takes place (Nitrogen or Ambient).

MARTIN (a Finetech company)

Microbial Nanocellulose Printed Circuit Boards for Medical Sensing

Technical Library | 2021-04-01 14:40:08.0

We demonstrate the viability of using ultra-thin sheets of microbially grown nanocellulose to build functional medical sensors. Microbially grown nanocellulose is an interesting alternative to plastics, as it is hydrophilic, biocompatible, porous, and hydrogen bonding, thereby allowing the potential development of new application routes. Exploiting

U.S. Naval Research Laboratory

iNEMI Project on Process Development of BiSn-Based Low Temperature Solder Pastes

Technical Library | 2021-05-13 16:09:02.0

The 2017 iNEMI Board and Assembly Roadmap forecasts that, due to economic, environmental and technical drivers, use of low temperature solder pastes will increase significantly and reach 10% of all solder paste used for board assembly by 2021.

iNEMI (International Electronics Manufacturing Initiative)

Conquering SMT Stencil Printing Challenges with Today's Miniature Components

Technical Library | 2023-06-12 16:52:47.0

The technological advancement of component and PCB technology from through-hole to surface mount (SMT) is a major factor in the miniaturization of today's electronics. Smaller and smaller component sizes and more densely packed PCBs lead to more powerful designs in much smaller product packages. With advancement, however, comes a new set of challenges in building these smaller, more complex assemblies. This is the challenge original equipment manufacturers (OEM) and contract manufacturers (CM) face today.

Fine Line Stencil, Inc.

MOS Scaling: Transistor Challenges for the 21st Century

Technical Library | 1999-05-07 08:50:40.0

To enable transistor scaling into the 21st century, new solutions such as high dielectric constaConventional scaling of gate oxide thickness, source/drain extension (SDE), junction depths, and gate lengths have enabled MOS gate dimensions to be reduced from 10mm in the 1970’s to a present day size of 0.1mm. To enable transistor scaling into the 21st century, new solutions such as high dielectric constant materials for gate insulation and shallow, ultra low resistivity junctions need to be developed. In this paper, for the first time, key scaling limits are quantified for MOS transistorsnt materials for gate insulation and shallow, ultra low resistivity junctions need to be developed.

Intel Corporation

Polyphenylene Ether Macromonomers. XI. Use in Non-Epoxy Printed Wiring Boards

Technical Library | 2012-11-01 20:54:49.0

First published in the 2012 IPC APEX EXPO technical conference proceedings. The continuous progression toward portable, high frequency microelectronic systems has placed high demands on material performance, notably low dielectric constants (Dk), low loss tangent (Df), low moisture uptake, and good thermal stability. Epoxy resins are the workhorses of the electronic industry. Significant performance enhancements have been obtained through the use of PPE telechelic macromonomers with epoxy resins. However, there is a ceiling on the performance obtainable from epoxy-based resins. Therefore, non-epoxy based dielectric materials are used to fulfill the need for higher performance.

SABIC

Advances in Conductive Inks across Multiple Applications and Deposition Platforms

Technical Library | 2012-12-27 14:35:29.0

Printed Electronics is generally defined as the patterning of electronic materials, in solution form, onto flexible substrates, omitting any use of the photolithography, etching, and plating steps commonly found within the Printed Circuit Board (PCB) industry. The origins of printed electronics go back to the 1960s, and close variants of several original applications and market segments remain active today. Through the 1980s and 1990s Printed Electronic applications based on Membrane Touch Switch and Electroluminescent lighting technologies became common, and the screen printed electronic materials used then have formed the building blocks for many of the current and emerging technologies and applications... First published in the 2012 IPC APEX EXPO technical conference proceedings.

DuPont

Board-Level Thermal Cycling and Drop-Test Reliability of Large, Ultrathin Glass BGA Packages for Smart Mobile Applications

Technical Library | 2018-08-22 14:05:42.0

Glass substrates are emerging as a key alternative to silicon and conventional organic substrates for high-density and high-performance systems due to their outstanding dimensional stability, enabling sub-5-µm lithographic design rules, excellent electrical performance, and unique mechanical properties, key in achieving board-level reliability at body sizes larger than 15 × 15 mm2. This paper describes the first demonstration of the board-level reliability of such large, ultrathin glass ball grid array (BGA) packages directly mounted onto a system board, considering both their thermal cycling and drop-test performances.

Institute of Electrical and Electronics Engineers (IEEE)

New Approaches to Develop a Scalable 3D IC Assembly Method

Technical Library | 2016-08-11 15:49:59.0

The challenge for 3D IC assembly is how to manage warpage and thin wafer handling in order to achieve a high assembly yield and to ensure that the final structure can pass the specified reliability requirements. Our test vehicles have micro-bumped die having pitches ranging from 60um down to 30um. The high density of pads and the large die size, make it extremely challenging to ensure that all of the micro-bump interconnects are attached to a thin Si-interposer. In addition, the low standoff between the die and interposer make it difficult to underfill. A likely approach is to first attach the die to the interposer and then the die/interposer sub-assembly to the substrate. In this scenario, the die/interposer sub-assembly is comparable to a monolithic silicon die that can be flip chip attached to the substrate. In this paper, we will discuss various assembly options and the challenges posed by each. In this investigation, we will propose the best method to do 2.5D assembly in an OSAT(Outsourced Assembly and Test) facility.

Invensas Corporation

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