Technical Library | 2012-01-12 22:51:19.0
In this paper, hollowed solder ball structures in wafer level packages are investigated. Detailed 3-D finite element modelling is conducted for stress and accumulated inelastic strain energy density or creep strain analysis. Three cases are studied in thi
Technical Library | 2008-02-26 15:02:19.0
More and more chip packages need multi-GHz RF structures to meet their performance targets. The ideal chip package needs to combine RF features with Digital features for these applications. They drive low-loss, controlled impedance transmission lines, flexibility in assigned signal and power layers, and clearances of various shapes in power layers. Building these features in a chip package is difficult without making the stack-up very thick or compromising the reliability of the product. In the present paper, we have designed and built a flip-chip package test vehicle (TV) to make new RF structures, using Z-axis interconnection (Zinterconnect) building blocks.
Technical Library | 2014-05-01 15:14:12.0
Bilayer graphene has been a subject of intense study in recent years. The interlayer registry between the layers can have dramatic effects on the electronic properties: for example, in the presence of a perpendicular electric field, a band gap appears in the electronic spectrum of so-called Bernal-stacked graphene. This band gap is intimately tied to a structural spontaneous symmetry breaking in bilayer graphene, where one of the graphene layers shifts by an atomic spacing with respect to the other. This shift can happen in multiple directions, resulting in multiple stacking domains with soliton-like structural boundaries between them
Technical Library | 2018-03-21 22:44:30.0
Solder paste printing is the first step in the surface mount manufacturing process for PCBA assembly. When the solder paste printing process is uncontrolled, defects can be produced, which may not become apparent until the PCBA is downstream. (...)This paper will discuss how Lean Six Sigma techniques were used to optimize the solder paste printing process. It will highlight how a cross-functional team used the structured Define, Measure, Analyze, Improve and Control (DMAIC) methodology to identify and control the critical inputs. The advantage of the Lean Six Sigma methodology is that it guides the team through the rigorous structured process so that all possible inputs are considered and the critical ones can be identified.
Technical Library | 2016-06-16 15:29:31.0
Embedding components within the PC board structure is not a new concept. Until recently, however, most embedded component PC board applications adapted only passive elements. The early component forming processes relied on resistive inks and films to enable embedding of resistor and capacitors elements. Although these forming methods remain viable, many companies are choosing to place very thin discrete passive components and semiconductor die elements within the PC board layering structure. In addition to improving the products performance, companies have found that by reducing the component population on the PC board's surface, board level assembly is less complex and the PC board can be made smaller, The smaller substrate, even when more complex, often results in lower cost. Although size and cost reductions are significant attributes, the closer coupling of key elements can also contribute to improving functional performance.This paper focuses on six basic embedded component structure designs described in IPC-7092.
Technical Library | 2016-07-14 18:21:29.0
Printed Circuit Boards (PCBs) and Printed Electronics (PE) both describe conductor/substrate combinations that make connections. Both PCB and PE technologies have been in use for a long time in one form or another with PCBs currently the standard for complex, high speed electronics and PE for user interface, complex form factor or other film based applications. New and innovative applications create the opportunity for promising structures. Taking advantage of the PCB shop's capability as well as the material set can help create these structures and indeed PE materials can find use in more traditional PCBs. New materials and new uses of existing materials open up many possibilities in electronic interconnecting structures. PCB manufacturers have a complex manufacturing infrastructure, well suited for both additive and subtractive conductor processing. While built around rigid material processing (flex PCB being the exception), there are opportunities for PE substrate processing. As electronics devices are applied to more and more parts of our lives, we need to continually push for better solutions. Fit, function, manufacturability, and cost are all important considerations. Crossing the PCB/PE boundary is a way to meet the challenge.
Technical Library | 2016-05-12 16:29:40.0
Advances in miniaturized electronic devices have led to the evolution of microvias in high density interconnect (HDI) circuit boards from single-level to stacked structures that intersect multiple HDI layers. Stacked microvias are usually filled with electroplated copper. Challenges for fabricating reliable microvias include creating strong interface between the base of the microvia and the target pad, and generating no voids in the electrodeposited copper structures. Interface delamination is the most common microvia failure due to inferior quality of electroless copper, while microvia fatigue life can be reduced by over 90% as a result of large voids, according to the authors’ finite element analysis and fatigue life prediction. This paper addresses the influence of voids on reliability of microvias, as well as the interface delamination issue.
Technical Library | 2016-09-15 17:10:40.0
This paper describes the purpose, methodology, and results to date of thermal endurance testing performed at the company. The intent of this thermal aging testing is to establish long term reliability data for printed wiring board (PWB) materials for use in applications that require 20+ years (100,000+ hours) of operational life under different thermal conditions. Underwriters Laboratory (UL) testing only addresses unclad laminate (resin and glass) and not a fabricated PWB that undergoes many processing steps, includes copper and plated through holes, and has a complex mechanical structure. UL testing is based on a 5000 hour expected operation life of the electronic product. Therefore, there is a need to determine the dielectric breakdown / degradation of the composite printed circuit board material and mechanical structure over time and temperature for mission critical applications.
Technical Library | 2019-12-26 19:13:52.0
Plated through hole (PTH) plays a critical role in printed circuit board (PCB) reliability. Thermal fatigue deformation of the PTH material is regarded as the primary factor affecting the lifetime of electrical devices. Numerous research efforts have focused on the failure mechanism model of PTH. However, most of the existing models were based on the one-dimensional structure hypothesis without taking the multilayered structure and external pad into consideration.In this paper, the constitutive relation of multilayered PTH is developed to establish the stress equation, and finite element analysis (FEA) is performed to locate the maximum stress and simulate the influence of the material properties. Finally, thermal cycle tests are conducted to verify the accuracy of the life prediction results. This model could be used in fatigue failure portable diagnosis and for life prediction of multilayered PCB.
Technical Library | 2021-01-21 02:04:27.0
Traditional single level microvia structures are generally considered the most robust type of interconnection within a printed wire board (PWB) substrate. The rapid implementation of HDI technology now commonly requires between 2, 3 or 4 levels of microvias sequentially processed into the product. Recent OEM funded reliability testing has confirmed that by increasing the levels (stack height) these structures are proving less reliable, when compared to their single or double level counterparts. Recently false positive results have been recorded on products tested with traditional thermal shock testing methodology (cycling between -40°C and 125°C, or 145°C). A number of companies are incurring product failures resulting in increased costs associated with replacing the circuit boards, components and added labour.
.jpg)