Technical Library | 2019-05-31 14:19:24.0
ACI Technologies (ACI) characterized the reliability of surface mount RF components. The RF frequency band of interest was the X band (10.7 to 11.7GHz). A two pronged test for reliability of circuit card assemblies (CCA) was designed for both extreme thermal cycling and vibration. The rapid thermal cycling and extreme vibration testing simulates the total stress encountered by the assembly over the life of the product but accomplishes it in a relatively short period of time. In order to perform the reliability testing, a test vehicle consisting of a printed circuit board with test structures and components, was designed, fabricated, and assembled at ACI.
Technical Library | 1999-05-06 14:39:20.0
ntelís traditional microprocessor test methodology, based on manually generated functional tests that are applied at speed using functional testers, is facing serious challenges due to the rising cost of manual test generation and the increasing cost of high-speed testers. If current trends continue, the cost of testing a device could exceed the cost of manufacturing it. We therefore need to rely more on automatic test pattern generation (ATPG) and low-cost structural testers.
Technical Library | 2018-07-25 21:37:11.0
This paper will discuss the expanded use of boundary-scan testing beyond the typical manufacturing test to capture structural defects on a component/devices in a printed circuit board assembly (PCBA). The following topics will be discussed to demonstrate the capability of boundary-scan test system on how we can extend beyond typical manufacturing test: Boundary-scan as a complete manufacturing test system, Boundary-scan implementation during PCBA design stage, Implementation of boundary-scan beyond typical structural testing
Technical Library | 2018-08-01 11:25:59.0
With complexities of PCB design scaling and manufacturing processes adopting to environmentally friendly practices raise challenges in ensuring structural quality of PCBs. This makes it essential to have a good 'Design for Test' (DFT) to ensure a robust structural test. (...)During the course of the DFT review, can we realize a good test strategy for the PCBA. How can the test strategy of the PCBA be partitioned as to what portions of the design can be covered structurally and what is covered functionally, in a way that provides best diagnostics to discover faults
Technical Library | 1999-08-05 10:34:17.0
This document defines a set of standard test structures with which to benchmark the electrostatic discharge (ESD) robustness of CMOS technologies. The test structures are intended to be used to evaluate the elements of an integrated circuit in the high current and voltage ranges characteristic of ESD events. Test structures are given for resistors, diodes, MOS devices, interconnects, silicon control rectifiers, and parasitic devices. The document explains the implementation strategy and the method of tabulating ESD robustness for various technologies.
Technical Library | 2016-09-15 17:10:40.0
This paper describes the purpose, methodology, and results to date of thermal endurance testing performed at the company. The intent of this thermal aging testing is to establish long term reliability data for printed wiring board (PWB) materials for use in applications that require 20+ years (100,000+ hours) of operational life under different thermal conditions. Underwriters Laboratory (UL) testing only addresses unclad laminate (resin and glass) and not a fabricated PWB that undergoes many processing steps, includes copper and plated through holes, and has a complex mechanical structure. UL testing is based on a 5000 hour expected operation life of the electronic product. Therefore, there is a need to determine the dielectric breakdown / degradation of the composite printed circuit board material and mechanical structure over time and temperature for mission critical applications.
Technical Library | 2008-02-26 15:02:19.0
More and more chip packages need multi-GHz RF structures to meet their performance targets. The ideal chip package needs to combine RF features with Digital features for these applications. They drive low-loss, controlled impedance transmission lines, flexibility in assigned signal and power layers, and clearances of various shapes in power layers. Building these features in a chip package is difficult without making the stack-up very thick or compromising the reliability of the product. In the present paper, we have designed and built a flip-chip package test vehicle (TV) to make new RF structures, using Z-axis interconnection (Zinterconnect) building blocks.
Technical Library | 2007-05-09 18:26:16.0
High Density Interconnect (HDI) technology is fast becoming the enabling technology for the next generation of small portable electronic communication devices. These methods employ many different dielectrics and via fabrication technologies. In this research, the effect of the proximity of microvias to Plated Through Holes (PTHs) and its effect on the reliability of the microvias was extensively evaluated. The reliability of microvia interconnect structures was evaluated using Liquid-To-Liquid Thermal Shock (LLTS) testing (-55oC to +125oC). Comprehensive failure analysis was performed on microvias fabricated using different via fabrication technologies.
Technical Library | 2013-11-27 16:54:01.0
The need in complexity for microwave space products such as active BFNs (Beam Forming Networks) is increasing, with a significantly growing number of amplitude / phase control points (number of beams * numbers of radiating elements). As a consequence, the RF component’s package topology is evolving (larger number of I/Os, interconnections densification ...) which directly affect the routing and architecture of the multilayer boards they are mounted on. It then becomes necessary to improve the density of these boards (...) This paper will present the work performed to achieve LCP-based high density multilayer structures, describing the different electrical and technological breadboards manufactured and tested and presenting the results obtained.
Technical Library | 2010-06-23 21:59:03.0
Quality control is one of the main bottlenecks in the production of micro-opto-electromechanical systems/microelectromechanical systems (MOEMS/MEMS) because each structure on a wafer is serially inspected and scanned stepwise over the entire wafer area.
