Technical Library | 2015-02-19 16:54:34.0
Pad cratering is an important failure mode besides crack of solder joint as it’ll pass the regular test but have impact on the long term reliability of the product. A new pin pull test method with solder ball attached and positioning the test board at an angle of 30º is employed to study the strength of pad cratering. This new method clearly reveals the failure mechanism. And a proper way to interpret the finite element analysis (FEA) result is discussed. Impact of pad dimension, width and angle of copper trace on the strength is included. Some findings not included in previous research could help to guide the design for better performance
Technical Library | 2019-02-06 22:02:08.0
The High Density Packaging (HDP) user group has completed a project to evaluate the majority of viable Dk (Dielectric Constant)/Df (Dissipation Factor) and delay/loss electrical test methods, with a focus on the methods used for speeds above 2 GHz. A comparison of test methods from 1 to 2 GHz through to higher test frequencies was desired, testing a variety of laminate materials (standard volume production with UL approval, low loss, and "halogen-free" laminate materials). Variations in the test board material resin content/construction and copper foil surface roughness/type were minimized. Problems with Dk/Df and loss test methods and discrepancies in results are identified, as well as possible correlations or relationships among these higher speed test methods.
Technical Library | 2016-09-22 17:52:59.0
Conformal Coatings are often used to increase the reliability of electronic assemblies operating in harsh or corrosive environments where the product would otherwise fail prematurely. Conformal coatings are often qualified to international standards, intended to enable users to better differentiate between suitable conformal coating chemistries, but always on a flat test coupon, which is not representative of real world use conditions. In order to better correlate international standards with real world-use conditions, three-dimensional Surface Insulation Resistance (SIR) test boards have been manufactured with dummy components representative of those commonly used on printed circuit assemblies...
Technical Library | 2015-12-17 17:24:17.0
Product quality can be improved through proper application of design for test (DFT) strategies. With today's shrinking product sizes and increasing functionality, it is difficult to get good test coverage of loaded printed circuit boards due to the loss of test access. Advances in test techniques, such as boundary scan, help to recover this loss of test coverage. However, many of these test techniques need to be designed into the product to be effective.This paper will discuss how to maximize the benefits of boundary scan test, including specific examples of how designers should select the right component, connect multiple boundary scan components in chains, add test access to the boundary scan TAP ports, etc. A discussion of DFT guidelines for PCB layout designers is also included. Finally, this paper will include a description of some advanced test methods used in in-circuit tests, such as vectorless test and special probing methods, which are implemented to improve test coverage on printed circuit boards with limited test access.
Technical Library | 2012-04-26 18:52:37.0
First presented at IPC Apex Expo 2012. The reliability, as tested by thermal cycling, of printed wire boards (PWB) are established by three variables; copper quality, material robustness and design. The copper quality was most influential and could be eva
Technical Library | 2010-09-02 13:13:03.0
As chip packaging and interconnectivity have become more dense and operate at higher clock frequencies, physical access for traditional bed-of-nails testing becomes limited. This results in loss of ICT (in-circuit test) fault coverage and higher test fi
Technical Library | 2018-06-20 13:11:57.0
Manufacturers test to ensure that the product is built correctly. Shorts, opens, wrong or incorrectly inserted components, even catastrophically faulty components need to be flagged, found and repaired. When all such faults are removed, however, functional faults may still exist at normal operating speed, or even at lower speeds. Functional board test (FBT) is still required, a process that still relies on test engineers’ understanding of circuit functionality and manually developed test procedures. While functional automatic test equipment (ATE) has been reduced considerably in price, FBT test costs have not been arrested. In fact, FBT is a huge undertaking that can take several weeks or months of test engineering development, unacceptably stretching time to market. The alternative, of selling products that have not undergone comprehensive FBT is equally, if not more, intolerable.
Technical Library | 2018-07-25 21:37:11.0
This paper will discuss the expanded use of boundary-scan testing beyond the typical manufacturing test to capture structural defects on a component/devices in a printed circuit board assembly (PCBA). The following topics will be discussed to demonstrate the capability of boundary-scan test system on how we can extend beyond typical manufacturing test: Boundary-scan as a complete manufacturing test system, Boundary-scan implementation during PCBA design stage, Implementation of boundary-scan beyond typical structural testing
Technical Library | 2010-06-10 21:01:48.0
This paper researches the effectiveness of the R.O.S.E. cleanliness testing process for dissolving and measuring ionic contaminants from boards soldered with no-clean and lead-free flux technologies.
Technical Library | 2020-11-29 22:06:45.0
Plastic laminates are increasingly used as interposers within chip packaging applications. As a component within the package, the laminate is subjected to package moisture sensitivity testing. The moisture requirements of chip packaging laminates are related to ambient moisture absorption and thermal cycling. Printed wiring board (PWB) laminates, however, are gauged on properties relating to wet processes such as resist developing, copper etching, and pumice scrubbing. Consequently, printed wiring board moisture absorption test methods differ from chip packaging test conditions.
winsouce.jpg)
