Technical Library | 2014-08-19 15:39:13.0
Understanding warpage of package attach locations on PCBs under reflow temperature conditions is critical in surface mount technology. A new industry standard, IPC 9641, addresses this topic directly for the first time as an international standard.This paper begins by summarizing the sections of the IPC 9641 standard, including, measurement equipment selection, test setup and methodology, and accuracy verification. The paper goes further to discuss practical implementation of the IPC 9641 standards. Key advantages and disadvantages between available warpage measurement methods are highlighted. Choosing the correct measurement technique depends on requirements for warpage resolution, data density, measurement volume, and data correlation. From industry experience, best practice recommendations are made on warpage management of PCB land areas, covering how to setup, run, analyze, and report on local area PCB warpage.The release of IPC 9641 shows that flatness over temperature of the package land area on the PCB is critical to the SMT industry. Furthermore, compatibility of shapes between attaching surfaces in SMT, like a package and PCB, will be critical to product yield and quality in years to come.
Technical Library | 2020-08-16 14:50:25.0
Not all desiccant bags are created or perform equally. Performance measures include: a) How long does desiccant last? b) How much are can be desiccated in a given area? c) How much moisture is retained, and or released back into the atmosphere? This article walks engineers through various test they can perform to determine efficacy. Additionally, the article highlight between adsorption vs adsorption.
Technical Library | 2014-01-23 16:49:55.0
As reliability requirements increase, especially for defense and aerospace applications, the need to characterize components used in electronic assembly also increases. OEM and EMS companies look to perform characterizations as early as possible in the process to be able to limit quality related issues and improve both assembly yields and ultimate device reliability. In terms of BGA devices, higher stress conditions, RoHS compatible materials and increased package densities tend to cause premature failures in intermetallic layers. Therefore it is necessary to have a quantitative and qualitative test methodology to address these interfaces.
Technical Library | 2007-05-09 18:26:16.0
High Density Interconnect (HDI) technology is fast becoming the enabling technology for the next generation of small portable electronic communication devices. These methods employ many different dielectrics and via fabrication technologies. In this research, the effect of the proximity of microvias to Plated Through Holes (PTHs) and its effect on the reliability of the microvias was extensively evaluated. The reliability of microvia interconnect structures was evaluated using Liquid-To-Liquid Thermal Shock (LLTS) testing (-55oC to +125oC). Comprehensive failure analysis was performed on microvias fabricated using different via fabrication technologies.
Technical Library | 2009-07-22 18:33:41.0
This paper deals with the thermal effects of joule heating in a high interconnect density, thin core, buildup, organic flip chip substrate. The 440 μm thick substrate consists of a 135 μm thick core with via density of about 200 μm. The typical feature sizes in the substrate are 50 micron diameter vias is the core/buildup layers and 12 micron thick metal planes. An experimental test vehicle is powered with current and the temperature rise was measured. A numerical model was used to simulate the temperature rise in the TV.
Technical Library | 2012-10-25 16:34:02.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper will examine stencil technologies (including Laser and Electroform), Aperture Wall coatings (including Nickel-Teflon coatings and Nano-coatings), and how these parameters influence paste transfer for miniature devices with Area Ratios less than the standard recommended lower limit of .5. A matrix of print tests will be utilized to compare paste transfer and measure the effectiveness of the different stencil configurations. Area Ratios ranging from .32 to .68 will be investigated.
Technical Library | 2017-06-29 16:39:30.0
Currently there is no industry standard test method for measuring dielectric properties of circuit board materials at frequencies greater than about 10 GHz. Various materials vendors and test labs take different approaches to determine these properties. It is common for these different approaches to yield varying values of key properties like permittivity and loss tangent. The D-24C Task Group of IPC has developed this round robin program to assess these various methods from the "bottom up" to determine if standardized methods can be agreed upon to provide the industry with more accurate and valid characteristics of dielectrics used in high-frequency and high-speed applications.
Technical Library | 2014-05-29 13:48:14.0
Electronics packaging based on stress-engineered spring interconnects has the potential to enable integrated IC testing, fine pitch, and compliance not readily available with other technologies. We describe new spring contacts which simultaneously achieve low resistance ( 30 μm) in dense 2-D arrays (180 ~ 180-µm pitch). Mechanical characterization shows that individual springs operate at approximately 150-µN force. Electrical measurements and simulations imply that the interface contact resistance contribution to a single contact resistance is This paper suggests that integrated testing and packaging can be performed with the springs, enabling new capabilities for markets such as multichip modules.
Technical Library | 2020-07-02 13:29:37.0
Industry standards such as J-STD-005 and JIS Z 3284-1994 call for the use of viscosity measurement(s) as a quality assurance test method for solder paste. Almost all solder paste produced and sold use a viscosity range at a single shear rate as part of the pass-fail criteria for shipment and customer acceptance respectively. As had been reported many times, an estimated 80% of the defects associated with the surface mount technology process involve defects created during the printing process. Viscosity at a single shear rate could predict a fatal flaw in the printability of a solder paste sample. However, false positive single shear rate viscosity readings are not unknown.
Technical Library | 2016-11-10 08:56:54.0
It goes without saying that every manufacturer wants to ensure they are producing a quality product. Standards and specifications from various organizations provide a guideline from which manufacturers can measure different areas of quality, while also providing the end user with the reassurance that they are purchasing a trustworthy, long-lasting product. Within the wire processing industry there are many standards that manufacturers may choose or be required to adhere to. These standards and specifications are constantly evolving and increasing in detail, especially as monitoring technology improves.
.gif)
.png)
