Technical Library | 2014-07-02 16:46:09.0
Growth behaviors of intermetallic compounds (IMCs) and Kirkendall voids in Cu/Sn/Cu microbump were systematically investigated by an in-situ scanning electron microscope observation. Cu–Sn IMC total thickness increased linearly with the square root of the annealing time for 600 h at 150°C, which could be separated as first and second IMC growth steps. Our results showed that the growth behavior of the first void matched the growth behavior of second Cu6Sn5, and that the growth behavior of the second void matched that of the second Cu3Sn. It could be confirmed that double-layer Kirkendall voids growth kinetics were closely related to the Cu–Sn IMC growth mechanism in the Cu/Sn/Cu microbump, which could seriously deteriorate the mechanical and electrical reliabilities of the fine-pitch microbump systems
Technical Library | 2012-12-13 21:20:05.0
First published in the 2012 IPC APEX EXPO technical conference proceedings. We investigated the micro-void formation of solder joints after reliability tests such as preconditioning (precon) and thermal cycle (TC) by varying the thickness of Palladium (Pd) in Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG) surface finish. We used lead-free solder of Sn-1.2Ag-0.5Cu-Ni (LF35). We found multiple micro-voids of less than 10 µm line up within or above the intermetallic compound (IMC) layer. The number of micro-voids increased with the palladium (Pd) layer thickness. Our results revealed that the micro-void formation should be related to (Pd, Ni)Sn4 phase resulted from thick Pd layer. We propose that micro-voids may form due to either entrapping of volatile gas by (Pd, Ni)Sn4 or creeping of (Pd, Ni)Sn4.
Technical Library | 2020-07-29 19:58:48.0
The majority of flexible circuits are made by patterning copper metal that is laminated to a flexible substrate, which is usually polyimide film of varying thickness. An increasingly popular method to meet the need for lower cost circuitry is the use of aluminum on Polyester (Al-PET) substrates. This material is gaining popularity and has found wide use in RFID tags, low cost LED lighting and other single-layer circuits. However, both aluminum and PET have their own constraints and require special processing to make finished circuits. Aluminum is not easy to solder components to at low temperatures and PET cannot withstand high temperatures. Soldering to these materials requires either an additional surface treatment or the use of conductive epoxy to attach components. Surface treatment of aluminum includes the likes of Electroless Nickel Immersion Gold plating (ENIG), which is extensive wet-chemistry and cost-prohibitive for mass adoption. Conductive adhesives, including Anisotropic Conductive Paste (ACP), are another alternate to soldering components. These result in component substrate interfaces that are inferior to conventional solders in terms of performance and reliability. An advanced surface treatment technology will be presented that addresses all these constraints. Once applied on Aluminum surfaces using conventional printing techniques such as screen, stencil, etc., it is cured thermally in a convection oven at low temperatures. This surface treatment is non-conductive. To attach a component, a solder bump on the component or solder printed on the treated pad is needed before placing the component. The Aluminum circuit will pass through a reflow oven, as is commonly done in PCB manufacturing. This allows for the formation of a true metal to metal bond between the solder and the aluminum on the pads. This process paves the way for large scale, low cost manufacturing of Al-PET circuits. We will also discuss details of the process used to make functional aluminum circuits, study the resultant solder-aluminum bond, shear results and SEM/ EDS analysis.
Technical Library | 2019-07-17 17:56:34.0
The increased demand for electronic devices in recent years has led to an extensive research in the field to meet the requirements of the industry. Electrolytic copper has been an important technology in the fabrication of PCBs and semiconductors. Aqueous sulfuric acid baths are explored for filling or building up with copper structures like blind micro vias (BMV), trenches, through holes (TH), and pillar bumps. As circuit miniaturization continues, developing a process that simultaneously fills vias and plates TH with various sizes and aspect ratios, while minimizing the surface copper thickness is critical. Filling BMV and plating TH at the same time, presents great difficulties for the PCB manufactures. The conventional copper plating processes that provide good via fill and leveling of the deposit tend to worsen the throwing power (TP) of the electroplating bath. TP is defined as the ratio of the deposit copper thickness in the center of the through hole to its thickness at the surface. In this paper an optimization of recently developed innovative, one step acid copper plating technology for filling vias with a minimal surface thickness and plating through holes is presented.
Technical Library | 2014-11-13 19:23:50.0
With increasing power loss of electrical components, thermal performance of an assembled device becomes one of the most important quality factors in electronic packaging. Due to the rapid advances in semiconductor technology, particularly in the regime of high-power components, the temperature dependence of the long-term reliability is a critical parameter and has to be considered with highest possible care during the design phase (...) The aim of this paper is to give a short overview about standard thermal solutions like thick copper, thermal vias, plugged vias or metal core based PCBs. Furthermore, attention will be turned on the development of copper filled thermal vias in thin board constructions...
Technical Library | 2016-05-19 16:03:37.0
As consumers become more reliant on their handheld electronic devices and take them into new environments, devices are increasingly exposed to situations that can cause failure. In response, the electronics industry is making these devices more resistant to environmental exposures. Printed circuit board assemblies, handheld devices and wearables can benefit from a protective conformal coating to minimize device failures by providing a barrier to environmental exposure and contamination. Traditional conformal coatings can be applied very thick and often require thermal or UV curing steps that add extra cost and processing time compared to alternative technologies. These coatings, due to their thickness, commonly require time and effort to mask connectors in order to permit electrical conductivity. Ultra-thin fluorochemical coatings, however, can provide excellent protection, are thin enough to not necessarily require component masking and do not necessarily require curing. In this work, ultra-thin fluoropolymer coatings were tested by internal and industry approved test methods, such as IEC (ingress protection), IPC (conformal coating qualification), and ASTM (flowers-of-sulfur exposure), to determine whether this level of protection and process ease was possible.
Technical Library | 2017-03-09 17:37:05.0
This article focuses on the fabrication and characterization of stretchable interconnects for wearable electronics applications. Interconnects were screen-printed with a stretchable silver-polymer composite ink on 50-μm thick thermoplastic polyurethane. The initial sheet resistances of the manufactured interconnects were an average of 36.2 mΩ/◽, and half the manufactured samples withstood single strains of up to 74%. The strain proportionality of resistance is discussed, and a regression model is introduced. Cycling strain increased resistance. However, the resistances here were almost fully reversible, and this recovery was time-dependent. Normalized resistances to 10%, 15%, and 20% cyclic strains stabilized at 1.3, 1.4, and 1.7. We also tested the validity of our model for radio-frequency applications through characterization of a stretchable radio-frequency identification tag.
Technical Library | 2019-05-15 22:26:02.0
As the demand for higher routing density and transfer speed increases, Via-In-Pad Plated Over (VIPPO) has become more common on high-end telecommunications products. The interactions of VIPPO with other features used on a PCB such as the traditional dog-bone pad design could induce solder joints to separate during the second and thereafter reflows. The failure has been successfully reproduced, and the typical failure signature of a joint separation has been summarized.To better understand the solder separation mechanism, this study focuses on designing a test vehicle to address the following three perspectives: PCB material properties, specifically the Z-direction or out-of-plane Coefficient of Thermal Expansion (CTE); PCB thickness and back drill depth; and quantification of the driving force magnitude beyond which the separation is due to occur.
Technical Library | 2023-11-14 19:52:11.0
The continuous drive in the Electronics industry to build new and innovative products has caused competitive design companies to develop assemblies with consolidated PCB designs, decreased physical sizes, and increased performance characteristics. As a result of these new designs, manufacturers of electronics are forced to contend with many challenges. One of the most significant challenges being the processing of thru-hole components on high thermal mass PCBs having the potential to exceed 20 layers in thicknesses and have copper mass contents of over 40oz. High thermal mass PCBs, coupled with the use of mixed technologies, decreased component spacing, and the change from Tin Lead Solder to Lead Free Alloys has lead many manufacturing facilities to purchase advanced soldering equipment to process challenging assemblies with a high degree of repeatability.
Technical Library | 2024-06-23 21:57:16.0
Two extremes of reflow time scale for copper pillar flip chip solder joints were explored in this study. Sn-2.5Ag solder capped pillars were joined to laminate substrates using either conventional forced convection reflow or the controlled impingement of a defocused infrared laser. The laser reflow joining process was accomplished with an order of magnitude reduction in time above liquidus and a similar increase in solidification cooling rate. The brief reflow time and rapid cooling of a laser impingement reflow necessarily affects all time and temperature dependent phenomena characteristic of reflowed molten solder. These include second phase precipitate dissolution, base metal (copper) dissolution, and the extent of surface wetting. This study examines the reflow dependent microstructural aspects of flip chip Sn-Ag joints on samples of two different size scales, the first with copper pillars of 70μm diameter on 120μm pitch and the second with 23μm diameter pillars on a 40μm pitch. The length scale of Pb-free solder joints is known to affect the Sn grain solidification structure; Sn grain morphology will be noted across both reflow time and joint length scales. Sn grain morphology was further found to be dependent on the extent of surface wetting when such wetting circumvented the copper diffusion barrier layer. Microstructural analysis also will include a comparison of intermetallic structures formed; including the size and number density of second phase Ag3Sn precipitates in the joint and the morphology and thickness of the interfacial intermetallics formed on the pillar and substrate surfaces.
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