Technical Library | 2015-02-27 17:06:01.0
The drive towards fine pitch technology also affects the soldering processes. Selective soldering is a reliable soldering process for THT (through hole) connectors and offers a wide process window for designers. THT connectors can be soldered on the top and bottom side of boards, board in board, PCBs to metal shields or housing out of plastic or aluminum are today's state of the art. The materials that are used to make the solder connections require higher temperatures. Due to the introduction of lead-free alloys, the boards need more heat to get the barrels filled with solder. This not only affects the properties of the flux and components, but the operation temperatures of solder machines become higher (...)First the impact of temperature will be discussed for the separate process steps and for machine tooling. In the experimental part measurements are done to verify the accuracy that can be achieved using today's selective soldering machines. Dedicated tooling is designed to achieve special requirements with respect to component position accuracy.
Technical Library | 2016-08-11 01:21:34.0
Be it a residential building, hospital, shopping mall, hotel, school, educational institution or any kind of a building, the security of the building is a prime facet to get a complete building solution. This also includes protecting the building, its assent and the human life from the airborne toxic industrial chemical, radiological and biological attacks or any accidental release apart from fire, water, earthquake and other security concerns. For these high value security solutions, the upgraded technology for the building safety system is now a top priority, especially in the commercial building sector and residential constructions. To introduce a completely new concept and a unique solution, it is necessary to focus on the dynamic electronic design and manufacturing solution in consultation with the custom PCB experts.
Technical Library | 2021-12-16 01:48:41.0
Package-on-Package (PoP) technology is widely used in mobile devices due to its simple design, lower cost and faster time to market. Warpage characteristic and requirement of PoP package becomes critical to ensure both the top and bottom package can be mounted with minimal yield lost. With this challenge in placed, iNEMI has been working relentlessly to fingerprint the current PoP package technology warpage characteristic and to establish some key learning for packaging technologies. The work also extended to understand the basic requirement needed for successful PoP stacking by analyzing the warpage data obtained and formulate a simple analytical equation to explain the true warpage requirement for PoP packaging.
Technical Library | 2021-12-16 01:52:32.0
Package on Packages (PoP) find use in applications that require high performance with increased memory density. One of the greatest benefits of PoP technology is the elimination of the expensive and challenging task of routing high-speed memory lines from under the processor chip out to memory chip in separate packages. Instead, the memory sits on top of the processor and the connections are automatically made during assembly. For this reason PoP technology has gained wide acceptance in cell phones and other mobile applications. PoP technology can be assembled using one-pass and two-pass assembly processes. In the one-pass technique the processor is first mounted to the board, the memory is mounted to the processor and the finished board is then run through the reflow oven in a single pass. The two-pass technique has an intermediate step in which the memory is first mounted onto the processor.
Technical Library | 2022-01-03 14:55:55.0
Follow Ted as he learns about the Maintenance Planner Scheduler job description in the excerpt below from the full Maintenance Planning and Scheduling course PowerPoint download. The course PowerPoint starts out teaching Ted that the Maintenance Planner Scheduler job opening is much more than being a preventive maintenance planner or being a maintenance repair person. As you will learn here, the potential planner needs to learn the big picture first. Like applying Lean Six Sigma principles and methodologies. © 2021 - Ref: https://bin95.com/articles/maintenance-management/preventive-maintenance-planner.htm
Technical Library | 2018-10-18 15:41:45.0
One specific market space of interest to emerging printed electronics is In Mold Label (IML) technology. IML is used in many consumer products and white good applications. When combined with electronics, the In Mold Electronics (IME) adds compelling new product functionality. Many of these products have multi-dimensional features and therefore require thermoforming processes in order to prepare the labels before they are in-molded. While thermoforming is not a novel technique for IML, the addition of printed electronic functional traces is not well documented. There is little or no published work on printed circuit performance and design interactions in the thermoforming process that could inform improved IME product designs. A general full factorial Design of Experiments (DOE) was used to analyze the electrical performance of the conductive silver ink trace/polycarbonate substrate system. Variables of interest include trace width, height of draw, and radii of both top and bottom curvatures in the draw area. Thermoforming tooling inserts were fabricated for eight treatment combinations of these variables. Each sample has one control and two formed strips. Electrical measurements were taken of the printed traces on the polymer sheets pre- and post- forming with a custom fixture to evaluate the effect on resistance. The design parameters found to be significant were draw height and bottom radius, with increased draw and smaller bottom curvature radii both contributing to the circuits’ resistance degradation. Over the ranges evaluated, the top curvature radii had no effect on circuit resistance. Interactions were present, demonstrating that circuit and thermoforming design parameters need to be studied as a system. While significant insight impacting product development was captured further work will be executed to evaluate different ink and substrate material sets, process variables, and their role in IME.
Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
Technical Library | 2023-06-12 19:00:21.0
The SMT print process is now very mature and well understood. However as consumers continually push for new electronic products, with increased functionality and smaller form factor, the boundaries of the whole assembly process are continually being challenged. Miniaturisation raises a number of issues for the stencil printing process. How small can we print? What are the tightest pitches? Can we print small deposits next too large for high mix technology assemblies? How closely can we place components for high density products? ...And then on top of this, how can we satisfy some of the cost pressures through the whole supply chain and improve yield in the production process! Today we are operating close to the limits of the stencil printing process. The area ratio rule (the relationship between stencil aperture opening and aperture surface area) fundamentally dictates what can and cannot be achieved in a print process. For next generation components and assembly processes these established rules need to be broken! New stencil printing techniques are becoming available which address some of these challenges. Active squeegees have been shown to push area ratio limits to new boundaries, permitting printing for next generation 0.3CSP technology. Results also indicate there are potential yield benefits for today's leading edge components as well. Stencil coatings are also showing promise. In tests performed to date it is becoming apparent that certain coatings can provide higher yield processing by extending the number of prints that can be performed in-between stencil cleans during a print process. Preliminary test results relating to the stencil coating technology and how they impact miniaturisation and high yield processing will be presented.
