Technical Library: voids (Page 3 of 6)

Effect of Cu–Sn intermetallic Compound Reactions on the Kirkendall Void Growth Characteristics in Cu/Sn/Cu Microbumps

Technical Library | 2014-07-02 16:46:09.0

Growth behaviors of intermetallic compounds (IMCs) and Kirkendall voids in Cu/Sn/Cu microbump were systematically investigated by an in-situ scanning electron microscope observation. Cu–Sn IMC total thickness increased linearly with the square root of the annealing time for 600 h at 150°C, which could be separated as first and second IMC growth steps. Our results showed that the growth behavior of the first void matched the growth behavior of second Cu6Sn5, and that the growth behavior of the second void matched that of the second Cu3Sn. It could be confirmed that double-layer Kirkendall voids growth kinetics were closely related to the Cu–Sn IMC growth mechanism in the Cu/Sn/Cu microbump, which could seriously deteriorate the mechanical and electrical reliabilities of the fine-pitch microbump systems

Nepes Corporation

Voids in Solder Joints

Technical Library | 2019-12-12 21:43:43.0

Presented at SMTA Boise Expo and Tech Forum, March 20, 2018

Intel Corporation

Solderability after Long-Term Storage

Technical Library | 2022-03-02 20:51:50.0

The effect of long-term storage on manufacturability and reliability is an area of major concern for companies that attempt to proactively manage component availability and obsolescence. A number of issues can arise depending on the technology and storage environment. Mechanisms of concern can include solderability, stress driven diffusive voiding, kirkendahl voiding, and tin whiskering. Of all of these, solderability / wettability remains the number one challenge in longterm storage.

DfR Solutions (acquired by ANSYS Inc)

Influence of Pd Thickness on Micro Void Formation of Solder Joints in ENEPIG Surface Finish

Technical Library | 2012-12-13 21:20:05.0

First published in the 2012 IPC APEX EXPO technical conference proceedings. We investigated the micro-void formation of solder joints after reliability tests such as preconditioning (precon) and thermal cycle (TC) by varying the thickness of Palladium (Pd) in Electroless Nickel / Electroless Palladium / Immersion Gold (ENEPIG) surface finish. We used lead-free solder of Sn-1.2Ag-0.5Cu-Ni (LF35). We found multiple micro-voids of less than 10 µm line up within or above the intermetallic compound (IMC) layer. The number of micro-voids increased with the palladium (Pd) layer thickness. Our results revealed that the micro-void formation should be related to (Pd, Ni)Sn4 phase resulted from thick Pd layer. We propose that micro-voids may form due to either entrapping of volatile gas by (Pd, Ni)Sn4 or creeping of (Pd, Ni)Sn4.

Samsung Electro-Mechanics

Reliability Study of Bottom Terminated Components

Technical Library | 2015-07-14 13:19:10.0

Bottom terminated components (BTC) are leadless components where terminations are protectively plated on the underside of the package. They are all slightly different and have different names, such as QFN (quad flat no lead), DFN (dual flat no lead), LGA (land grid array) and MLF (micro lead-frame. BTC assembly has increased rapidly in recent years. This type of package is attractive due to its low cost and good performance like improved signal speeds and enhanced thermal performance. However, bottom terminated components do not have any leads to absorb the stress and strain on the solder joints. It relies on the correct amount of solder deposited during the assembly process for having a good solder joint quality and reliable reliability. Voiding is typically seen on the BTC solder joint, especially on the thermal pad of the component. Voiding creates a major concern on BTC component’s solder joint reliability. There is no current industry standard on the voiding criteria for bottom terminated component. The impact of voiding on solder joint reliability and the impact of voiding on the heat transfer characteristics at BTC component are not well understood. This paper will present some data to address these concerns.

Flex (Flextronics International)

Influence of Plating Quality on Reliability of Microvias

Technical Library | 2016-05-12 16:29:40.0

Advances in miniaturized electronic devices have led to the evolution of microvias in high density interconnect (HDI) circuit boards from single-level to stacked structures that intersect multiple HDI layers. Stacked microvias are usually filled with electroplated copper. Challenges for fabricating reliable microvias include creating strong interface between the base of the microvia and the target pad, and generating no voids in the electrodeposited copper structures. Interface delamination is the most common microvia failure due to inferior quality of electroless copper, while microvia fatigue life can be reduced by over 90% as a result of large voids, according to the authors’ finite element analysis and fatigue life prediction. This paper addresses the influence of voids on reliability of microvias, as well as the interface delamination issue.

CALCE Center for Advanced Life Cycle Engineering

The Morphology Evolution and Voiding of Solder Joints on QFN Central Pads with a Ni/Au Finish

Technical Library | 2012-10-18 21:58:51.0

First published in the 2012 IPC APEX EXPO technical conference proceedings. In this paper, we report on a comprehensive study regarding the morphology evolution and voiding of SnAgCu solder joints on the central pad of two different packages – QFN and an Agilent package called TOPS – on PCBs with a Ni/Au surface finish.

Agilent Technologies, Inc.

Assessing the Effectiveness of I/O Stencil Aperture Modifications on BTC Void Reduction

Technical Library | 2018-09-26 20:33:26.0

Bottom terminated components, or BTCs, have been rapidly incorporated into PCB designs because of their low cost, small footprint and overall reliability. The combination of leadless terminations with underside ground/thermal pads have presented a multitude of challenges to PCB assemblers, including tilting, poor solder fillet formation, difficult inspection and – most notably – center pad voiding. Voids in large SMT solder joints can be difficult to predict and control due to the variety of input variables that can influence their formation. Solder paste chemistries, PCB final finishes, and reflow profiles and atmospheres have all been scrutinized, and their effects well documented. Additionally, many of the published center pad voiding studies have focused on optimizing center pad footprint and stencil aperture designs. This study focuses on I/O pad stencil modifications rather than center pad modifications. It shows a no-cost, easily implemented I/O design guideline that can be deployed to consistently and repeatedly reduce void formation on BTC-style packages.

AIM Solder

Moisture Effect on Properties of Out-of-Autoclave Laminates with Different Void Content

Technical Library | 2020-12-16 18:38:49.0

Fabrication of large structures using out-of-autoclave prepreg materials will lead to a great amount of savings in manufacturing costs. In the out-of-autoclave processing method, the presence of voids inside the laminate has been an issue due to the lack of high pressure during manufacturing. This study aims primarily to observe the moisture absorption response of composite samples containing different levels of void. By changing the vacuum level inside the bag during the manufacturing process, three different unidirectional laminates at three levels of void have been manufactured. After immersing the samples in warm water at 60°C for about one year, the moisture absorption level was monitored and then diffusion coefficients were calculated using Fick's law. Results show that the moisture absorption coefficient changes by %8 within the experimental range of void contents. The mechanical behaviour of these laminates has been studied at four different moisture levels by performing dynamic mechanical analysis (DMA) and short beam shear tests. Empirical results indicate that, in general, interlaminar shear strength and glass transition temperature decrease by moisture build-up inside the samples. DiBenedetto equation is proposed to make a correlation between the moisture content and glass transition temperature.

Concordia University

Pad Design and Process for Voiding Control at QFN Assembly

Technical Library | 2024-07-24 01:04:35.0

Quad Flat No Leads (QFN) package designs receive more and more attention in electronic industry recently. This package offers a number of benefits including (1) small size, such as a near die size footprint, thin profile, and light weight; (2) easy PCB trace routing due to the use of perimeter I/O pads; (3) reduced lead inductance; and (4) good thermal and electrical performance due to the adoption of exposed copper die-pad technology. These features make the QFN an ideal choice for many new applications where size, weight, electrical, and thermal properties are important. However, adoption of QFN often runs into voiding issue at SMT assembly. Upon reflow, outgassing of solder paste flux at the large thermal pad has difficulty escaping and inevitably results in voiding. It is well known that the presence of voids will affect the mechanical properties of joints and deteriorate the strength, ductility, creep, and fatigue life. In addition, voids could also produce spot overheating, lessening the reliability of the joints.

Indium Corporation


voids searches for Companies, Equipment, Machines, Suppliers & Information

Best SMT Reflow Oven

World's Best Reflow Oven Customizable for Unique Applications
Win Source Online Electronic parts

Training online, at your facility, or at one of our worldwide training centers"
Online Equipment Auction Jabil Monterrey MX Aug 19, 2024

Component Placement 101 Training Course
PCB Handling with CE

Stencil Printing 101 Training Course
Electronic Solutions R3

Private label coffee for your company - your logo & message on each bag!