Electronics Forum: /02 (Page 1141 of 1286)

PCB lamination issues

Electronics Forum | Mon Feb 12 11:12:16 EST 2007 | davef

Q1. After reflow some boards start producing bumps/bubbles which damage the internal layers causeing PCBs failed in Electrical-testing. How can I eradicate this problem from my assembling process? A1. Find a proper board supplier. Q2. If SMT compon

simple doubt about reflow profile

Electronics Forum | Mon Feb 12 13:16:35 EST 2007 | CK the Flip Guy

Looks good at first glance. Couple of questions, though: Time Above _____. Fill in the blank. Is Liquidous 183C (Tin-Lead) or 217C to 220C (Lead Free)? The "soak" of 150-190, at 0.6*C per second ramp up looks good, weather it's lead or lead-free

simple doubt about reflow profile

Electronics Forum | Sun Feb 18 16:47:34 EST 2007 | darby

As I stated, the reply was direct from Indium, (thanks to Rich Brooks). The information regarding cool down rates should come from your paste supplier; not an oven supplier; not a generic article on lead free. I just went through the data sheets from

SMT on Flexible circuits

Electronics Forum | Fri Feb 16 06:47:38 EST 2007 | CL

vshan, We were using pallets (delmat with cavities for the flex) We put stips of double sided Kapton tape in the critical areas. The tape held up to the heat and kept the circuit flat for the QFP's and BGA's. We based our assembly process for this c

Solder Printing 2x2 inch ceramic Substrate

Electronics Forum | Thu Feb 15 16:58:11 EST 2007 | flipit

Phil, I used to print solder paste on 2" X 2" and 3" X 3" 96% Alumina substrates all the time. I used standard solder printers and stencils. Screens are difficult to use and don't print well. You can use a stencil on a DeHart, CW Price, or AMI Pr

Fuji IP-1 won't vision read PQFP64 package - any ideas?

Electronics Forum | Thu Feb 15 15:23:12 EST 2007 | bvdb

The IP-1 vision error is" "Processing Error" er 401F 4003 which the FIP-I Operating Manual says the cause is "The actual number of leads on the part exceeds the number of leads in the Part Data". I have checked and re-checked the part data, lead

Stencil apertures for SOT639-2 package

Electronics Forum | Mon Feb 19 10:04:21 EST 2007 | realchunks

It's a nasty little part, but usuallu solders well. Now your inspectors will thing it's not soldered and try and touch it up, but generally, the exposed leads are not tinned, and will not toe fillet. If they know this up front they won't over heat

GSM VME upgrade options?

Electronics Forum | Tue Feb 20 06:31:58 EST 2007 | mika

It depends on what VME box build it is. Rev. C, D, E etc. There are upgrade kits for the complete VME chassi and it includes some re-wiring also. For this You must contact UIC and provide them with the machine ser.nr, current Os-system, UPS s/w ver.

Wave

Electronics Forum | Wed Feb 21 15:16:52 EST 2007 | wavemasterlarry

sure sounds like alot of over kill. You can get all the info you need by running your machine. Keep the dross cleamed outof it and replace the flux stone every so often and you shouldn't have any problems. Them fancy machines are no match for real

Lead manufacturing to lead free transisition

Electronics Forum | Tue Feb 27 12:16:19 EST 2007 | wavemasterlarry

hahaha! LISTEN, everyone knows that oven get dirty. They need periodic cleaning. So if you run lead boards thru your oven you will get lead dust and residue in you're oven. If you want to be truely lead free you need to get all the lead outta of


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