Electronics Forum | Thu Nov 13 09:27:21 EST 2008 | cisridn
I have tried covering the vias with thermal tape and that did not work. I like the idea of plugging the via with a temporary solder mask. I will try that the next time I build a fixture which should be tomorrow. This is mainly a problem only becau
Electronics Forum | Fri Nov 14 17:21:17 EST 2008 | cisridn
Plugging the holes with temporary solder mask helped some, but once the solder starts to reflow, the fumes from the flux pushed the solder mask out. What I ended up doing in addition to using the temporary solder mask was covering the areas of pcb w
Electronics Forum | Tue Nov 18 09:52:56 EST 2008 | cisridn
Fortunately, I only have one more set of boards left. I may or may not have to assembly, I have not gotten the word yet. Anyway, it would be good to know how to rework the boards with SR1000. I usually do not have any input when design team spins a
Electronics Forum | Wed Nov 12 14:46:58 EST 2008 | hutch770
Greetings all, I'm pretty new to the SMT world, having been a class 10 fab monkey in my previous life. What I'm looking for is recommendations for pneumatic lead cutters. I need them to flush-cut as close as possible to the via without destroying
Electronics Forum | Thu Nov 13 11:45:04 EST 2008 | pbarton
We have seen a similar problem. Turned out to be mechanical stress on the component caused by the method of location and clamping at ICT. Where is the component located on the assembly? Poorly adjusted clamping pillars on clamshell fixtures can cause
Electronics Forum | Thu Nov 13 20:24:30 EST 2008 | snsmt
Right now, I am mostly getting .pho (gerber files) and .asc (pads) but i don't have anything to convert it to excel or text files so that Cad2cad can read it. I have camtastic! 2000, but i haven't figured out a way to convert it. I want to able to e
Electronics Forum | Fri Nov 14 02:18:04 EST 2008 | act_smt
What is the spec or true classification for the leads for an Electrolytic capacitor? Is it a : 1)Flattened coined lead??? or 2)Flat Lug Lead??? There is some confusion as to how we should be inspecting & accepting the toe overhang on these per IP
Electronics Forum | Tue Nov 18 20:03:19 EST 2008 | davef
Here are people at IPC that can direct you to the people you need to talk to about the issues that you have with the standards: * Jack Crawford, IOM, IPC Director Certification and Assembly Technology, crawja@ipc.org 847-597-2893, 847-615-5693 * Dav
Electronics Forum | Tue Dec 02 07:56:40 EST 2008 | realchunks
Wow, rocket science with Nasa specs! I like it. I don't see the trick question here, so I'll continue.... IPC simply states over hang of round or flattened (coined) leads is acceptable (class 1, 2, & 3) if it "does not violate minimum electrical c
Electronics Forum | Tue Nov 18 07:22:56 EST 2008 | wewilldoit
Hi folks! TI told us that we are the only one with the following problem... We discovered a really bad wetting characteristic of some SMD ICs from BurrBrown. At the moment: XTR106 / INA118 / ADS7844. After the reflow process we found out that this pa
