Electronics Forum | Thu Mar 10 09:13:15 EST 2005 | davef
From http://www.IPC.org ... IPC-7351 - Generic Requirements for Surface Mount Land Pattern and Design Standard The successor to the IPC-SM-782A is here! The document covers land pattern design for all types of passive and active components, includ
Electronics Forum | Thu Mar 10 23:23:56 EST 2005 | pmd
We have a MyData TP-9-2 with a in line Y wagon. It is a long screw and the vintage is 1994. The Y wagon vibrates at about 24 micrometers at about 25 hertz. Burnin reviels zero encoder pulse errors. Hystersis test indicates a Y axis Y wise varance of
Electronics Forum | Sun Mar 13 23:30:59 EST 2005 | VS
After reflow AOI makes sense because it has the highest coverage of the defects. Problems like tombstone, lifted pins, open solder joints, some shorts and insufficient solder you will not find before oven. I would also not agree with the statement th
Electronics Forum | Thu Mar 17 06:56:41 EST 2005 | Grant
Hi, Even if you don't use vision or a HYDRA head, the MYDATA should still sense no component, and try 3 times by default. Also, if the MYDATA does not place the component it will not be marked as places, so the placement program won't ever finish. Y
Electronics Forum | Mon Mar 21 09:33:25 EST 2005 | davef
RoHS Substance||RoHS MCV Limits||Typical Testing Approaches Lead||1000 ppm* ||Wet chemical digestion followed by ICP (Inductively coupled plasma) or AAS (atomic absorption) spectroscopy ||||XRF (X-ray fluorescence) spectroscopy Cadmium||100 ppm ||Wet
Electronics Forum | Wed Mar 16 09:06:07 EST 2005 | russ
This is what I might do, I would purchase either a solder volume (preferred) or at the least a paste height measurement piece of equipmment, The most important parameters with pronting are volume and registration. You need one of these inspection
Electronics Forum | Tue Mar 15 07:59:07 EST 2005 | mattkehoe
We are looking for some feedback on this situation. Please let us know if you have any ideas. Thanks in advance. I have been doing some studies on defects and such with our PCB's in prep for lead free and I've come to a conclusion about our process.
Electronics Forum | Tue Mar 15 09:46:06 EST 2005 | davef
Comments are: * J-STD-001 and A-610 committees have eliminated the requirement that solder joints be "bright and shiny". Certain metallizations (such as gold) can influence the solder joint surface texture, but have no impact of reliability. Reliance
Electronics Forum | Wed Mar 16 09:22:20 EST 2005 | russ
Try varying you conveyor speed as well to increase the dwell time on the wave (touchy, and can easily be overdone). Every no-clean type and process I have ever used will leave some type of residue. They can be minimized but they will always be ther
Electronics Forum | Wed Mar 16 20:11:03 EST 2005 | darby
KT, What sort of delta T are you getting? This does sound a bit odd. TCs are in EXACTLY the same position on each board? Something I only recently found out - according to Mark Cannon from ERSA re profiling, that you may wish to consider. 1.TCs sho
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