Electronics Forum | Wed Dec 21 11:33:22 EST 2022 | SMTA-64304420
Does anyone have experience with HiP defects with DDR memory components that they would be willing to share? I am interested in SMT process corrective actions and repair processes. I can discuss this privately if needed.
Electronics Forum | Fri Apr 07 05:10:29 EDT 2023 | abhishek10
Reverse Polarity Defect in diode.what could be the reason and how to avoid it. We have the issue facing in NPM and CM machines of panasonic.Any investigation would help.
Electronics Forum | Fri Jun 30 15:12:36 EDT 2023 | tommy_magyar
A bridge is a defect. Full stop. If you are working in contract manufacturing, talk to the customer and get approval from them to accept it. They will not refuse unless there are high risks involved. If you are building your own products, then have
Electronics Forum | Wed Mar 14 18:29:04 EST 2001 | mparker
The basic rule of thumb (info current as of 9/2000, from Ceeris and others) is the 10X multiplier for each major process step. Catching a defect and correcting in SMT will cost $0.10 each. (think about $.04 placement cost, stop line time, operator h
Electronics Forum | Mon Sep 23 03:12:01 EDT 2002 | surachai
We encounter this problem also , I know that it 's acceptable per IPC standard but sometime it fail at ICT and FCT , then this problem should be prevent , we found it with QFP 16 mil pitch and the defect looklike negative wetting at the front of lead
Electronics Forum | Wed Jul 20 15:05:28 EDT 2005 | Fred M.
With the new rev D release of IPC-A_610 came a new section 10.2.9.3 which identifies a via (through hole) with nicks along the inside of the annular ring. Defect is all three classes and states "Damage to conductor or lands". We have for years defa
Electronics Forum | Tue May 29 16:52:07 EDT 2001 | hussman
By far the easiest way is to track solder paste measurement on your board - or solder defects after reflow (key word- easiest). Why spend 2 weeks examining a stencil when it clearly doesn't make defects, or IS making defects. I find using 2-D data
Electronics Forum | Wed Nov 18 10:39:48 EST 1998 | Scott Lolmaugh
| | | Does sombbody know what DPM rate a good and reliable SMT assembly line (incl. solder paste print, assembly and feflow soldering) has? | | | | | Chris, | | It may be helpful if you could translate DPM into a meaningful phrase as many people (my
Electronics Forum | Wed Apr 27 11:43:32 EDT 2005 | patrickbruneel
Hi Daan, What we did in the time was pareto analyses on all board designs to determine the critical areas (mainly design errors) and only inspect those specific problem areas. Every batch had a copy of the PC board with problem areas marked and only
Electronics Forum | Mon Jan 08 20:33:15 EST 2001 | Kyung Sam Park
Where can I find this kinds of S/W for SMT PROCESS. With defects collected for each smtline Analyze the cause of defect using D/B in smt process automatically(DB means cause of defects in smt process already prepared with for a long period ex
