Electronics Forum: fabricators (Page 56 of 85)

Etchback

Electronics Forum | Wed Oct 19 07:44:33 EDT 2005 | davef

When a hole is drilled during board fabrication, it can transfer resin from the base material (eg, FR4 core or prepreg) to cover the exposed edge of conductive material in the wall of a drilled hole. This is called resin smear. Etchback is a control

What's The Dealy-O With Smocks?

Electronics Forum | Tue Dec 20 16:56:53 EST 2005 | rsmith

I manufacture ESD supplies such as smocks and conduct ESD audits from time to time. With that said, here is my deal on smocks...ESD smocks work well to shield harmful static charges on clothing such as wool, silk, and synthetic fabrics. It is like we

Standard for Stencil printers edges pressure

Electronics Forum | Tue Apr 18 19:48:08 EDT 2006 | davef

There is no standard, nor should there be [because the IPC standards should be aimed at describing results, not the path used to reach the results]. So, your printer equipment supplier recommendations are a good starting point. Your "35-46 lbs-in"

Pcb immersion tin thickness

Electronics Forum | Wed Aug 09 08:06:07 EDT 2006 | davef

See "IPC-4554 Specification for Immersion Tin Plating for Printed Circuit Boards" 3.2.1 Immersion Tin Thickness. The most common reason for solderability issues with the white tin surface coating during multiple thermal excursions is a thin white ti

Do yo have to bake unused bare boards or just Vacuum Pack?

Electronics Forum | Thu Aug 24 15:54:13 EDT 2006 | davef

It depends. What is: * Storage environment and period * Board laminate, epoxy, and copper thickness of PTH * Down stream process * Etc FR4 0.062" thick boards absorb between 0.08 to 0.1%Wt of moisture within a 24 hour period, and 0.2 to 0.23%Wt in

Glass Wicking

Electronics Forum | Sat Nov 11 11:27:51 EST 2006 | Tom

Hi, "glass wicking failure" we don't know what this is, but we suspect that the reflow process could very well be the root cause for some of our pcba with micro vias failure. Micro vias pcb we know to well (we don't like them at all). There are No p

Design rule for vias

Electronics Forum | Wed Dec 06 21:28:12 EST 2006 | davef

It's worse than just using the test equipment manufacturer guidelines. Along with that, you have to deal with each of the test fixture fabricators' preferences as well. What this boils down to is a negotiation with the test engineering group as to w

Question about pad pullbacks

Electronics Forum | Mon Dec 18 11:17:52 EST 2006 | mashmo

I am always looking for ways to make my boards more reliable and easier to fabricate and assemble. I have been baselining my footprints off of IPC-7351 and with the latest revision of the calculator they have started a new feature. Normally on say

Automate goldfinger masking?

Electronics Forum | Sun Dec 31 07:31:40 EST 2006 | davef

Thoughts are: * Eliminate solder spotting on gold fingers through process improvement in broard handling, printing paste control, and reflow recipe development. Search the fine SMTnet Archives for previous discussions. * Dispense or print a reflow te

PCB lamination issues

Electronics Forum | Mon Feb 12 11:12:16 EST 2007 | davef

Q1. After reflow some boards start producing bumps/bubbles which damage the internal layers causeing PCBs failed in Electrical-testing. How can I eradicate this problem from my assembling process? A1. Find a proper board supplier. Q2. If SMT compon


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