Electronics Forum | Thu Nov 04 23:45:16 EST 1999 | Jeff Sanchez
Hey Brian, We are not sure what it is you are referring too? If you feel they did not respond promptly than I am assuming that you picked up the phone and asked them what's up? Your thread just came across as bashing and a little negative, as
Electronics Forum | Tue Oct 26 18:03:05 EDT 1999 | Dave F
Sai: I can't amswer your questions, but I can give you some leads to people that may be able to help you. Below is a list of companies that deal used equipment. Some refurbish equipment, others turn the equipment from seller to buyer. Good luck.
Electronics Forum | Thu Oct 21 09:56:11 EDT 1999 | Brian
Rich An excellent question and one which is often totally ignored. If you wish a "no-clean" flux to be as safe as it possibly can be, the PCB and the components must all be contamination free (ionic and non-ionic). Only then can you be sure that the
Electronics Forum | Mon Oct 11 13:44:29 EDT 1999 | Dave F
Ken: Since Earl is no longer here, I guess I'll bite on this. Your questions are very broad and difficult to answer specifically. So, I'll give you broad and non-specific answers. | Hi, | | We are using mixed technology in our PCBA. Would like to
Electronics Forum | Sun Oct 10 17:40:50 EDT 1999 | JohnW
| | | Is there an IPC Standard stating the max. number of times that a PCB can pass through a reflow or wavesolder machine without having solder mask breakdown. | | | | | | PCB is FR4 | | | Solder Mask is LPI | | | Reflow and W/S Profile = Standard
Electronics Forum | Wed Oct 06 04:23:09 EDT 1999 | Brian
| | I am a new employee at a company that has had a large turnover of employees over the past year. I am working on a board (components on one side only), the engineer (he is also new ) wants to use an .035 pad with a .021 dia. hole, there are no via
Electronics Forum | Wed Oct 06 12:03:12 EDT 1999 | Graham Naisbitt
| | Hi, | | | | Help! Could anyone help to enlighten me on this? | | | | Question: | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z that using a n
Electronics Forum | Wed Oct 06 23:36:28 EDT 1999 | karlin
| | | Hi, | | | | | | Help! Could anyone help to enlighten me on this? | | | | | | Question: | | | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowable Y/Z or X/Z
Electronics Forum | Fri Oct 08 02:31:07 EDT 1999 | Brian
| | | | Hi, | | | | | | | | Help! Could anyone help to enlighten me on this? | | | | | | | | Question: | | | | | | | | If I have a CSP/BGA package of size X by Y and the standoff gap between the component and PCB is Z, What is the maximum allowab
Electronics Forum | Tue Oct 05 01:22:46 EDT 1999 | Karlin
| I am working on trying to define a cost per placement measure in our SMT assembly operations. | | Does anyone know where I might find a published industry average that we may compare to? | | I�ve heard it stated that an industry average is less t
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