Electronics Forum | Mon May 13 06:15:12 EDT 2019 | dhanish
how to control warpage on panelized pcb during reflow process.we are already running with pallet.Encountering problem to insert the pcb into pallet after first reflow cycle.The insertion is being done by robotic arm. Any recommendation on the profile
Electronics Forum | Thu May 23 10:21:19 EDT 2019 | emeto
What is the material of this PCB?
Electronics Forum | Mon Jul 01 04:39:49 EDT 2019 | sssamw
yes, You need tell us how the PCB and board designed, size, material, how de-paneling the PCB?
Electronics Forum | Mon May 13 23:44:26 EDT 2019 | dami0629
if use tray cannot solve the problem, you can change from the design 1）Reduce the effect of temperature on PCB 2) PCB USE HIGH TG 3) BOARD THICKNESS TOO THIN 4) MODIFY THE BOARD SIZE 5) Reduce the V-CUT depth.
Electronics Forum | Mon Jul 01 09:33:08 EDT 2019 | dbuschel
if you can't change the PCB materials or design at this point, you might be able to reduce it somewhat through the use of fixtures or edge stiffeners. Unless it is a particularly thick board, I don't think the reflow profile would be the issue. The t
Electronics Forum | Mon May 13 06:38:41 EDT 2019 | relaycz
You need to give us a little more information. 1. What is the size of your panel? 2. Are there any heavy components? 3. What is the thickness of your board panel? 4. What kind of oven are you using? 5. Is it only a recent problem or ongoing one?
Electronics Forum | Thu Oct 14 04:28:29 EDT 1999 | Grace Chua
Hi there, I have quite a number of problematic bd due to warpage problem. I would like to know the method on how to measure PCB warpage, thus to decide on the dispositon of these boards. Another question, can these warp bd be rework/fix. Is there
Electronics Forum | Fri Oct 15 11:05:50 EDT 1999 | Mark Phinney
Earliar we had problems with board warpage, Much of our problem was due to imbalances in the copper on oppisite layers in brief on a 8 layer board the copper on layer 1 should = the copper on layer 8, 2=7, 3=6, 4 = 5. We added copper to some layers t
Electronics Forum | Thu Oct 14 20:42:07 EDT 1999 | Jeff Ferry
Grace, As deifned in IPC 7721 Procedure 3.2 Bow and Twist Repair "Bow and twist after soldering shall not exceed 1.5% for through hole PC boards and .75% for surface mount PC boards. The bow and twist shall not be sufficient to cause difficulties d
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