Electronics Forum | Mon Aug 30 16:10:10 EDT 1999 | Dave F
| I have looked through the IPC web page and surfed to frustration. Can somebody give me a lead? | Brian: We don't use an etched board. We use a special stencil, described below and print on bare copper laminate. 3 Solder Wetting Test. Recogniz
Electronics Forum | Thu Aug 26 14:45:09 EDT 1999 | Earl Moon
| What are the key steps to achieving high yield with CSP ??? | | (We are trying qualify vendors for volume fab/assembly of some | products which use several CSP devices on each side of the | board. (Some with 0.5mm ball pitch)) | | Looking throu
Electronics Forum | Sat Aug 28 08:41:12 EDT 1999 | Tom Tellinghuisen
Wolfgang, We also tried to find generic 'guidelines' for Moisture Sensitivity levels. It would be a perfect world, if you could say that all PLCC84's were level 4 devices. Unfortunately it is not that easy. Moisture sensitivity levels are
Electronics Forum | Wed Aug 25 10:49:42 EDT 1999 | Boca
| | Again, I really appreciate the valuable input you all provided. Got my Air-Vac SRM4 machine Friday afternoon. Stored it safely in my cube over the week-end for safe keeping. Tried to find 220V single phase next to air with no luck yesterday. Elec
Electronics Forum | Tue Aug 24 05:11:32 EDT 1999 | George Verboven
| | Hello everyone, | | We found many cylindrical diodes missing during SMT process. Could someone tell us how to prevent this problem? Is it effective to change the shape of stencil apture or reduce fan speed in reflow oven? Thanks in advance. | |
Electronics Forum | Tue Aug 31 19:16:59 EDT 1999 | Steve Surtees
| I am looking for a rule of thumb regarding the maximum ramp standard components (chip capacitors) can tolerate without failure during the reflow process. The standard seems to be 3C\second, but this figure is generally derived from the average ram
Electronics Forum | Tue Aug 31 20:41:45 EDT 1999 | Dreamsniper
| | I am looking for a rule of thumb regarding the maximum ramp standard components (chip capacitors) can tolerate without failure during the reflow process. The standard seems to be 3C\second, but this figure is generally derived from the average r
Electronics Forum | Sun Aug 22 08:21:39 EDT 1999 | Earl Moon
| | | Want to know the Tools/ Process required to get started with CSP prototyping and R & D. | | | Anyone working on this , please help out. | | | | | Depending on the type, size, and pitch - just like BGA's, they aren't tough. Our 1mm types went t
Electronics Forum | Mon Aug 23 11:27:00 EDT 1999 | Dave F
0.6 �m (25 micro inches) and self-limit around 5 mils depending on the material being plated and the process. Similarly with white tin, laminates with cleaned copper are immersed in a series of tin baths without an external source of electric curren
Electronics Forum | Wed Aug 18 15:09:48 EDT 1999 | John Thorup
| OK folks, let's get real serious. | | Well, I shot off my big mouth yesterday during a scheduling meeting concerning DFM and rework. Again, what an irony, oxymoron, or that other thing. | | Anyway, I said it would take another 4 weeks to develop
