Electronics Forum | Tue Sep 21 13:24:17 EDT 2004 | GS
Hello, does any one please can tell me if any Standard says how much is the Total Ion Contamination ( ugr/NaCl sqcm equivalent, Br- in particular way) allowed on Connector surface/body ? (ie. DIMM connectors, and similar). Many Thanks in advan
Electronics Forum | Sat Sep 25 03:44:38 EDT 2004 | GS
Thanks Davef, unfotunately in order to keep TIC of PBA inside our customer TIC requirements, we have to pre-wash (DI water only)connectors before assembly. Too high level of Br- continuosly get released by connectors molding compound. Our assemb
Electronics Forum | Fri Oct 01 13:37:27 EDT 2004 | rkevin
Well Thanks for all the good advise. Lots of different opinions on this one. I took the advise to contact my current supplier of solder paste. They sent in one of their tech people along with a sales guy and we ran without much trouble. Other than a
Electronics Forum | Mon Oct 04 11:47:00 EDT 2004 | HOSS
We are trying to deploy an Ionograph cleanliness tester and wanted to know what others are using as a standard test sample. My desire is to run the test on a weekly basis using the same medium complexity assembly. We plan to use the testing as a pr
Electronics Forum | Tue Oct 05 17:37:21 EDT 2004 | mikecollier
We currently use a KIC 2000 system to profile on our oven and create our recipes. I had a customer in today reviewing our profiles, and he had concerns that we were exceeding 4 deg. c/sec. on our profiles. The process window parameters that we use
Electronics Forum | Thu Oct 28 08:26:40 EDT 2004 | curious
What are the defects you see when the stencil is over 50 n/cm? I can't recall ever seeing a (stencil caused) defect that wasn't a dent, ding or some other physical damage, and I would have a very hard time sending back a stencil that is working fine,
Electronics Forum | Tue Oct 26 03:12:36 EDT 2004 | Joseph
Dear all, Recently our production encountered high SOIC failure during testing after reflow soldering. All solder fillets (side/heel) are acceptable as per IPC standard.The reject samples (SOIC)being sent to IC manufacturer to verify the failure. Fin
Electronics Forum | Wed Nov 03 09:42:31 EST 2004 | dramos1
Hi Simon, Thanks for the immediate reply. We really appreciate it very much. Currently, we are using Class 2 for the visual inspection criteria of our telecom boards. In IPC-A-610 Rev. C criteria, there are TARGET, ACCEPTABLE and REJECT criterias.
Electronics Forum | Mon Jan 10 18:16:32 EST 2005 | ricardof
Greetings from Mexico I can see several good opinions about the "real" need to chnage to Lead-Free processes, but at the end and trying to be real, is there any good path we could follow to stop this process? I can see a lot of work, investment in eq
Electronics Forum | Wed Dec 22 19:09:17 EST 2004 | rohman23
Very strange...I just logged into the internet to come post this very question for all the lurking experts. We have a 16 layer rigid-flex that we have never baked. Our board vendor is expressing concern that we do not perform a pre-bake before assy
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