Electronics Forum | Tue Jun 08 11:54:17 EDT 1999 | Steve Skinner
| | | I'm encountering a new problem at my new company that I haven't encountered before in my past life - and that's Wave Soldering VIA holes. | | | | | | We've been getting a rash of defects that we call in this company, "insufficient solder in VI
Electronics Forum | Thu May 17 07:36:40 EDT 2001 | Bob Willis
Here is a copy of a draft document on PIHR Inspection I have jotted down on a flight to Scotland yesterday, any comments suggestions etc ? I have already most of the photos for the standard but as you know there is nothing in the IPC document it just
Electronics Forum | Wed Jun 30 09:33:11 EDT 1999 | Earl Moon
| | | | | | snip | | | | | | | John and Dave, | | | | | | | | Again, I don't work with larger chip devices with this issue. The company I now work with developed a strategy, based on considerable research (as others of us did in the past), to do t
Electronics Forum | Fri Jan 15 16:55:50 EST 1999 | Chrys
| | | Hello, | | | | | | We are qualifying new sources of PWB vendors. We've got the first lot of "produciton" boards in and we want to put them through the paces before turing the vendors on. | | | | | | So far, the tests I can think of performin
Electronics Forum | Thu Jul 13 22:20:38 EDT 2000 | Dave F
=10 mils larger than lead 3 silk screen legend text weight >=10 mils 4 pads >=15 mils larger than finished hole sizes 5 place through hole components on 50 mil grid 6 no silk screen legend text over vias (if vias not solder masked) or holes 7 so
Electronics Forum | Wed May 27 14:35:52 EDT 1998 | Justin Medernach
| | R&D is currently designing a board with smt components on both sides of the board. They are adding a 16 pin IC Gull wing. on the bottom side of the board. I have asked for only caps and resistors to be placed on the bottom side. Is there a recomm
Electronics Forum | Tue Jan 12 17:51:41 EST 1999 | Tom Gervascio
I've been using selective soldering process for about 18 months. The major problem concerns tight spacing- the distance between the SMT pads to be masked and the thru hole leads to be wave soldered should be no less than 0.150 inches. Keep the wall
Electronics Forum | Tue Nov 11 17:35:08 EST 2008 | davef
SM-840, is a material qualification document only, with all the test requirements applicable only to a defined test coupon, not to production boards. So, it's useless for what you're trying to accomplish. As assemblers use A-610 - Acceptability Of E
Electronics Forum | Wed Aug 09 22:11:46 EDT 2000 | Dave F
Mark: The best routing of test vias for BGAs is to keep them far away from the device. We route test pads for the outer two rows of balls and use vias as test pads for the inner rows of balls. Your bottom-side layout is fine. Yes, on the top-side
Electronics Forum | Wed Feb 14 21:14:45 EST 2001 | davef
BGA Shorting 1 Damaged mask in between the BGA pad and via on the substrate. 2 Poor print registration. 3 Poor via segregation from the pads? Are they tented or is there just a dam in between? 4 Review the profile. You can run into a number of p
