Electronics Forum | Wed Mar 24 11:09:44 EDT 2010 | rajeshwara
Hello Sir I faced the same problem for QFP in DTH product in India. IPC stated that void should not be more than 25% of solder joint. But this type of void definatly create problem during functional test. Please check the folloeing point... 1.Check t
Electronics Forum | Thu Mar 25 11:30:33 EDT 2010 | Sean
Hello Rajeshwara, If not mistaken, the 25% solder void specification is for BGA...As I I as know, no specification given to mosfet component yet..I think you are right, I need to look at the stencil aperture in order to reduce the air trap underneat
Electronics Forum | Tue Sep 04 02:28:17 EDT 2007 | philip_yam
Any one has experience over solder voids in oscillator capacitor joint could result in high phase noise during the digital performances test? The noise signal was gone after solder touch up. What could be the root cause of the high phase noise?
Electronics Forum | Thu Mar 25 12:34:26 EDT 2010 | bgaguy
the voids will cause a long term relability problem as the part will not be correctly heatsinked. Change your stencil aperature to a "+" sign 15-20 mils wide in the center of the pad. ___________ : | : : | : :----|----: : | : :__
Electronics Forum | Fri Mar 26 00:57:05 EDT 2010 | 89jeong
Hello Sir. We also have faced a same problem. At that time, we had to repair it because we could not find any solution. But in our experience, the void underneath FET was more severe whenever we used the FET that have been made long time ago. It is
Electronics Forum | Fri Mar 26 03:24:01 EDT 2010 | ravikumarasahitec
Hi, yes we used to see this kind of problem our customer end. This due to stencil aperture opening.these kind of issues we will overcome thorough our stencil process. please contact. ravikumar@asahitec.in
Electronics Forum | Tue Sep 04 10:27:33 EDT 2007 | rgduval
I haven't experienced this problem, exactly, but I have had issues with noise in digital circuits that appear to have gone away with touch up. The problem was that the customer blamed the noise issue on the solder quality, and he pointed to the fact
Electronics Forum | Thu Aug 15 15:58:12 EDT 2002 | robertnguyen
To whom this may concern, I recently ran into the problem with vias on pads of BGA when place BGA and reflow gas trap on vias escape and result in ball having void greater than 50% of BGA diameter. The BGA pad is measured at 20 mils and the vias mea
Electronics Forum | Fri Aug 16 09:59:49 EDT 2002 | dason_c
We baked the board first and print 2 mil water soluble paste at the BGA location and reflow. Wash and baked before the production run.
Electronics Forum | Fri Aug 16 10:00:03 EDT 2002 | davef
You have a very bad situation. It�s tough for the gas, flux material, er whatever to escape when the BGA is sitting on top of it and the blind via is blocking it from the other side. Obviously the vias should have been: * Placed on the edge of the
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