Aug 13, 2002
The PB (perimeter Bump or Bond) series from K&S Flipchip Division is now available from Practical Components and are designed to simulate the I/O of CMOS-like devices of various pad pitches. These are used as a die standard to evaluate flip chip applications as a function of various bump, materials or assembly materials. A limited number have been designed for wire bond evaluations.
The PB6 test chip is designed with I/O pads on 6 mil (152 micron) pitch located on the peripheral of the die. The 0.2-inch by 0.2-inch PB6 die contains 112 pads giving 56 daisy chain pairs.
The wafer size is 5-inch (125mm) with a die thickness of 600 to 650 microns. Die sizes available are .200x200, .400x.400 and .400x.600. Die are available with a number of options including various solder formulations and bump options.
