Device control via internal JTAG access - processor and FPGA cores While many ICs are equipped with a JTAG (IEEE Std. 1149.1) boundary-scan register (BSR), a significant number of microprocessors and DSPs can be found with deficient or even non-exi
Technical Library | 2015-12-02 18:32:50.0
(Thermal Compression with Non-Conductive Paste Underfill) Method.The companies writing this paper have jointly developed Copper (Cu) Pillar micro-bump and TCNCP(Thermal Compression with Non-Conductive Paste) technology over the last two+ years. The Cu Pillar micro-bump and TCNCP is one of the platform technologies, which is essentially required for 2.5D/3D chip stacking as well as cost effective SFF (small form factor) package enablement.Although the baseline packaging process methodology for a normal pad pitch (i.e. inline 50μm) within smaller chip size (i.e. 100 mm2) has been established and are in use for HVM production, there are several challenges to be addressed for further development for commercialization of finer bump pitch with larger die (i.e. ≤50μm tri-tier bond pad with the die larger than 400mm2).This paper will address the key challenges of each field, such as the Cu trace design on a substrate for robust micro-joint reliability, TCNCP technology, and substrate technology (i.e. structure, surface finish). Technical recommendations based on the lessons learned from a series of process experimentation will be provided, as well. Finally, this technology has been used for the successful launching of the company FPGA products with SFF packaging technology.
New Equipment | Component Programming
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81250A Main features 1 GHz (upgradeable) 4 analog channels 3-in-1 instrumentation: oscilloscope, logic analyzer and protocol analyzer 20 Mpts memory per channel to capture more data, and memory upgradeable to 1 Gpts 20 GSa/s sampling rate and I
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E8403A Main features 1 GHz (upgradeable) 4 analog channels 3-in-1 instrumentation: oscilloscope, logic analyzer and protocol analyzer 20 Mpts memory per channel to capture more data, and memory upgradeable to 1 Gpts 20 GSa/s sampling rate and In
Industry News | 2001-12-14 15:08:35.0
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Industry News | 2010-10-30 02:18:28.0
Lattice Semiconductor Corporation announced its new PAC-Designer® design software version 6.0, which enables analog and board designers to integrate a circuit board’s power management and digital board management functions into the newly announced Platform Manager™ device family.
