Electronics Forum | Thu Aug 21 09:01:46 EDT 2003 | caldon
Dan- We here do double sided reflow: we place one side and reflow....place the other side and reflow. On the second flow the underside of the PCB- we will reduce the bottom side preheat. fortunatly for us the largest component we only place a 40pin P
Electronics Forum | Thu Aug 08 15:16:03 EDT 2002 | OhioD
A "Pumpprint" stencil refers to a thick DEK stencil with pockets routed-out on the underside, so it will clear any THT leads, paste/glue deposits, etc., and not squish them. It's called pummprint because it was developed to use the ProFlow-type head
Electronics Forum | Wed Apr 26 03:32:29 EDT 2006 | saaitk
Hi all, Has anyone any experience they can share with regard to pad dissolution on PTH's on thick boards. We are using lead free SAC305 on both OSP and Immersion silver finishes and are experiencing difficulties when removing and replacing connector
Electronics Forum | Mon Jun 26 08:57:17 EDT 2017 | capse
If N2 is not an option, the cut wire feeder or drilled wire are your best bet for now. You need to optimize wire feed rate as well. The solder joint on the robot takes about the same time to form as in manual soldering. If you need to speed the solde
Electronics Forum | Fri Jun 11 03:14:03 EDT 2010 | muarty
Thanks Dax, We currently employ a stencil aperture design pretty much similar to that you describe. And you are correct in what you say about the thermal demands almost dictating the allowable voiding level. We have suggested to our customer that th
Electronics Forum | Fri Feb 22 18:36:36 EST 2013 | austinpeterman
Has anyone experienced bridging on topside (solder destination side) surface mount devices after wave soldering? We x-rayed 100% of the placements after smt re-flow with no issues. When the same placements were x-rayed after the tht wave solder pro
Electronics Forum | Mon Mar 25 21:50:10 EST 2002 | davef
Some of this was copped from Fred. There are numerous package types that now fall under the rubric of land grid array [LGA]. Land grid devices [ie, Bumped Chip Carrier� [BCC], LGA, Quad Flat-pack No-lead [QFN], MicroLeadFrame�, etc] are essentially
Electronics Forum | Fri Nov 11 13:52:05 EST 2011 | SheanDalton
What is the size of the low standoff components you find trace wash effluent? and, what is the gap from the board to the underside of the component? If your component has a very low standoff, and/or, a wide footprint, you may want to consider findi
Electronics Forum | Fri Feb 16 09:30:38 EST 2007 | DEK Answer Guy
Hello PR, PumpPrint� technologies enable high throughput adhesive deposition using a screen printing platform. Careful selection of stencil material, and informed study of the design of apertures and other stencil features, enables a wide range of
Electronics Forum | Tue Jun 05 03:56:52 EDT 2001 | JohnW
Flip Chip/uBGA Underfill Visual Standards The aim of this document is to produce some draft text and then select photographs to make up a draft visual standard for inspection. There is also a need to produce some reference material for C Scan image