Electronics Forum | Sat Sep 09 08:21:36 EDT 2000 | Sal
guys Currently experienced this problem on a product which had been running satifactorily for a period of time. No process changes were made, The problem was highlighted when after ICT when the boards were loaded in to the stress chamber, after the
Electronics Forum | Wed Aug 04 20:06:24 EDT 2004 | C.W
Customer returned a brd claim that one of the FPGA is having "cold solder joint". I inspected the the BGA location with X-ray and Ersascope, balls' shape look fine, voids are not detected, perimeter joints show shinny and smooth appearance, i have se
Electronics Forum | Mon Mar 12 10:29:07 EDT 2007 | george
Are you using wave solder pallets? I use same flux and solder as you do. I've seen this problem when some walls in the wave fixture cause a "shadowing effect"...if you enlarge those openings you will increase the dwell time eliminatting voids (if the
Electronics Forum | Sat Sep 21 23:38:06 EDT 2002 | ivanchu
I got one problem from my production line recently. One 0.5mm pitch QFP IC have been used on my PCBA. Actually, the defect was happened in randomly. Sometime, we got the fillet completely but sometime is not. The solder joint look like is good, but t
Electronics Forum | Sun Sep 22 09:36:04 EDT 2002 | davef
Sometimes the cut end of QFP leads have corrosion that is very difficult to solder. If this is what you're talking about, it is not a defect according A-610C, 6.5.2, Exposed Basis Metal
Electronics Forum | Tue Sep 24 12:58:27 EDT 2002 | dragonslayr
Although focusing on solderability may be the right answer, I wonder if you are satisfied that co-planarity is not the root cause. With random events of contact opens, this may be the case. Cleanliness of the stencil can also be a source of your pr
Electronics Forum | Tue Sep 24 07:42:36 EDT 2002 | Yannick
Hi, In your message ou talk about the QFP toe, we have some problems with that in our facilitie, Do you have some ideas to solve thise kind of problem? Thank You Yannick
Electronics Forum | Sat Sep 28 05:30:44 EDT 2002 | ivanchu
Stencil cleaning process is taking by machine every 15 boards. We are using wet, vaccune, Dry, Dry cleaning process. The aperture of the stencil is fullfil the aspect ratio.
Electronics Forum | Mon Sep 23 22:31:48 EDT 2002 | davef
Comments are: * It�s interesting, but not surprising that your time above liquidous varies around the sides of this component. * You are correct in thinking that it is better to reduce than to increase the temperature differences around the component
Electronics Forum | Mon Sep 23 03:12:01 EDT 2002 | surachai
We encounter this problem also , I know that it 's acceptable per IPC standard but sometime it fail at ICT and FCT , then this problem should be prevent , we found it with QFP 16 mil pitch and the defect looklike negative wetting at the front of lead
