Electronics Forum: solder and paste (Page 595 of 752)

Re: Cure/Reflow Profile

Electronics Forum | Tue Feb 22 11:53:16 EST 2000 | JAX

Sal, To answer your first statement; Yes, you can cure paste and reflow solder using one profile. Question on your second statement; Are you talking about running passive side glue, flipping it over, running active side solder, and then putting the

Re: Cure/Reflow Profile

Electronics Forum | Tue Feb 22 11:53:16 EST 2000 | JAX

Sal, To answer your first statement; Yes, you can cure paste and reflow solder using one profile. Question on your second statement; Are you talking about running passive side glue, flipping it over, running active side solder, and then putting the

dendritic growth

Electronics Forum | Tue Dec 14 07:32:57 EST 2004 | davef

On contaminated assemblies: While you isolated part of your dendritic growth to contaminated boards, could it be that you have a similar problem with other components, rather than your flux? Is this flux new? Have you had similar problems with thi

QFN84 Solder Printing Issue (QFN with Inner LGA Pad)

Electronics Forum | Fri Dec 01 14:40:02 EST 2017 | emeto

Very interesting pictures. It shows paste height of 200um - which is at lest 6mil stencil deposit. That on the other hand posts another question. Can you measure the ground pad level in relation to the solder mask level with the SPI? I had assemblies

Re: Tombstoning

Electronics Forum | Tue Feb 23 16:05:46 EST 1999 | Randy Haller

| What to look for that causes tombstoning and the corective action. | 1:check reflow profile 2:reduce pad size 3:reduce deposition of paste(stencil thickness/opening of aperatures) 4:Check components for solderability Good Luck

Gold plated PCB's

Electronics Forum | Thu May 09 15:56:33 EDT 2002 | stownsend

We are using NC. Paste doesn't seem to have an effect on the solderability on a bad batch of ENIG. When ENIG has gone bad, throw the board out.

Uneven thermal load in PCB design.

Electronics Forum | Tue Dec 17 18:37:18 EST 2002 | davef

As a starting point, consider that these component leads may not be getting hot enough. Measure the temperature profile on the leads that do not solder well to be sure: * Heating and cooling ramps are within the paste supplier's recommendations. * C

No Clean OSP process cause ICT testing issue due to Flux building in testvia hole

Electronics Forum | Fri Mar 29 07:53:12 EDT 2019 | davef

Why are you printing paste on test via? In the old days, we probed soldered pads to cushion impact force of probing. Is that still a reasonable practice?

Component drop after reflow

Electronics Forum | Thu Jun 27 08:12:17 EDT 2019 | SMTA-John

If the case shield is solderable, add pads to the edge of the two through holes and paste . This wetting should hold it in place.

First-Pass Yield Information

Electronics Forum | Fri Jul 06 18:21:24 EDT 2001 | davef

Maybe someone else can help, like: http://www.ceeris.com/efficiency.htm. Check with the following SMTnetters: * Steve Gregory. He posted a thread within the past week or so on solderability testing. He used to work at a memory module manufacturer


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