Technical Library | 2009-11-05 11:17:32.0
Head-in-pillow (HiP), also known as ball-and-socket, is a solder joint defect where the solder paste deposit wets the pad, but does not fully wet the ball. This results in a solder joint with enough of a connection to have electrical integrity, but lacking sufficient mechanical strength. Due to the lack of solder joint strength, these components may fail with very little mechanical or thermal stress. This potentially costly defect is not usually detected in functional testing, and only shows up as a failure in the field after the assembly has been exposed to some physical or thermal stress.
Technical Library | 2023-07-25 16:50:02.0
Some of the new handheld communication devices offer real challenges to the paste printing process. Normally, there are very small devices like 01005 chip components as well as 0.3 mm pitch uBGA along with other devices that require higher deposits of solder paste. Surface mount connectors or RF shields with coplanarity issues fall into this category. Aperture sizes for the small devices require a stencil thickness in the 50 to 75 um (2-3 mils) range for effective paste transfer whereas the RF shield and SMT connector would like at least 150 um (6 mils) paste height. Spacing is too small to use normal step stencils. This paper will explore a different type of step stencil for this application; a "Two-Print Stencil Process" step stencil. Here is a brief description of a "Two-Print Stencil Process". A 50 to 75 um (2-3 mils) stencil is used to print solder paste for the 01005, 0.3 mm pitch uBGA and other fine pitch components. While this paste is still wet a second in-line stencil printer is used to print all other components using a second thicker stencil. This second stencil has relief pockets on the contact side of the stencil any paste was printed with the first stencil. Design guidelines for minimum keep-out distances between the relief step, the fine pitch apertures, and the RF Shields apertures as well relief pocket height clearance of the paste printed by the first print stencil will be provided.
Technical Library | 2023-01-17 17:16:43.0
A test program was developed to evaluate the effectiveness of vacuum reflow processing on solder joint voiding and subsequent thermal cycling performance. Area array package test vehicles were assembled using conventional reflow processing and a solder paste that generated substantial void content in the solder joints. Half of the population of test vehicles then were re-processed (reflowed) using vacuum reflow. Transmission x-ray inspection showed a significant reduction in solder voiding after vacuum processing. The solder attachment reliability of the conventional and vacuum reflowed test vehicles was characterized and compared using two different accelerated thermal cycling profiles. The thermal cycling results are discussed in terms of the general impact of voiding on solder thermal fatigue reliability, results from the open literature, and the evolving industry standards for solder voiding. Recommendations are made for further work based on other void reduction methods and additional reliability studies.
Technical Library | 2023-05-22 17:46:29.0
Over the past several years, much research has been performed and published on the benefits of stencil nano-coatings and solvent under wipes. The process improvements are evident and well-documented in terms of higher print and end-of-line yields, in improved print volume repeatability, in extended under wipe intervals, and in photographs of the stencil's PCB-seating surface under both white and UV light. But quantifying the benefits using automated Solder Paste Inspection (SPI) methods has been elusive at best. SPI results using these process enhancements typically reveal slightly lower paste transfer efficiencies and less variation in print volumes to indicate crisper print definition. However, the improvements in volume data do not fully account for the overall improvements noted elsewhere in both research and in production.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
Technical Library | 2014-03-27 14:50:01.0
Because of the phase out of CFC's and HCFC's, standard solder pastes and fluxes evolved from RA and RMA fluxes, to No-Clean, to low residue No-Clean, to very low residue No-Clean. Many companies came out with their cleaning solutions, aqueous and semi-aqueous, with each product release being more innovative than the previous one. Unfortunately for most of the suppliers of cleaners, two other trends appeared; lead-free soldering and the progressive miniaturization of electronic devices.
Technical Library | 2022-02-16 15:34:32.0
Because of the phase-out of CFCs and HCFCs, standard solder pastes and fluxes evolved from RA and RMA fluxes to No-Clean, to low residue No-Clean, to very low residue No-Clean. Many companies came out with their cleaning solutions, aqueous and semi-aqueous, with each product release being more innovative than the previous one. Unfortunately for most of the suppliers of cleaners, two other trends appeared; lead-free soldering and the progressive miniaturization of electronic devices
Technical Library | 2023-05-22 16:49:42.0
Our customers' issues • Apertures are getting smaller • Paste does not release as well • Contaminates the bottom of the stencil • Increases defects / reduces yield Insufficient solder Bridging Solder balls on surface of PCB Flux residue • Requires more frequent cleaning • Reduced efficiency (wasted time) • Increased use of consumables (cost) USC fabric (use "cheap" fabric to reduce cost) Lint creates more defects Cleaning chemistries (use IPA to reduce cost) IPA breaks down flux and can create more defects
Technical Library | 2023-06-12 19:46:10.0
Solder paste printing is understood to be the leading contributor of defects in the electronics assembly process. Because yield accounts for such a large percentage of the margin, the greatest opportunity to improve profitability in the assembly of most electronics can be gained by reducing or eliminating solder defects. This article examines process adjustments made through stencil design that correct a misalignment situation between the PCB and stencil, leading to a 43% reduction in assembly defects. Examples of each are found in Table 1.
Technical Library | 2017-07-13 16:16:27.0
Controlled humidity and temperature controlled surface insulation resistance (SIR) measurements of flux covered test vehicles, subject to a direct current (D.C.) bias voltage are recognized by a number of global standards organizations as the preferred method to determine if no clean solder paste and wave soldering flux residues are suitable for reliable electronic assemblies. The IPC, Japanese Industry Standard (JIS), Deutsches Institut fur Normung (DIN) and International Electrical Commission (IEC) all have industry reviewed standards using similar variations of this measurement. (...) This study will compare the results from testing two solder pastes using the IPC-J-STD-004B, IPC TM-650 2.6.3.7 surface insulation resistance test, and IPC TM-650 2.3.25 in an attempt to investigate the correlation of ROSE methods as predictors of electronic assembly electrical reliability.
