Technical Library: doe (Page 4 of 6)

Electronic Does Not Equal Smart: Service Documentation and Brand Quality

Technical Library | 2018-02-01 00:31:48.0

This paper briefly summarizes the technologies underpinning the evolution in electrical system diagnosis and repair, which include schematic layout automation using prototypes and rule-based styling, instant language translation, 2D/3D view links with schematics, interactive diagnostic procedures, and dynamically-generated signal-tracing diagrams. These technologies empower after-sales service teams with state-of-the-art capabilities, which not only reduce costs but also improve brand quality in the eyes of its customers.

Mentor Graphics

How Does Surface Finish Affect Solder Paste Performance?

Technical Library | 2021-07-06 21:13:36.0

The surface finishes commonly used on printed circuit boards (PCBs) have an effect on solder paste performance in the surface mount process. Some surface finishes are non-planar like hot air solder level (HASL) which can lead to inconsistencies in solder paste printing. Other surface finishes are difficult to wet during reflow like organic solderability preservative (OSP). What is the overall effect of surface finish on solder paste performance? Which solder paste is best for each surface finish? It is the goal of this paper to answer these questions.

FCT ASSEMBLY, INC.

What Does Industry 4.0 Actually Deliver Today? Example Reflow.

Technical Library | 2021-08-04 18:41:30.0

Industry 4.0 is one of the most exciting developments in the manufacturing industry in decades. It promises vast improvements for both manufacturers and their customers. For some companies, however, it can be overwhelming, and it can be difficult with the current available information to understand exactly what the benefits will be in the average factory, and to calculate the return on the investment. Therefore, it may be helpful to bring the discussion down to a tangible level and to isolate one little part of the whole smart electronic assembly factory, namely reflow.

KIC Thermal

Pin in Paste Stencil Design for Notebook Mainboard

Technical Library | 2008-03-18 12:36:31.0

This paper examines the construction of a notebook mainboard with more than 2000 components and no wave soldering required. The board contains standard SMD, chipset BGAs, connectors, through hole components and odd forms placed using full automation and soldered after two reflow cycles under critical process parameters. However, state of the art technology does not help if the process parameters are not set carefully. Can all complex BGAs, THTs and even screws be soldered on a single stencil? What will help us overcome bridging, insufficient solder and thombstoning issues? This paper will demonstrate the placement of all odd shape components using pin-in-paste stencil design and full completion of the motherboard after two reflow cycles.

Vestel Electronic

Investigation of Pad Cratering in Large Flip-Chip BGA using Acoustic Emission

Technical Library | 2013-01-03 20:27:54.0

Electronics assemblies with large flip-chip BGA packages can be prone to either pad cratering or brittle intermetallic (IMC) failures under excessive PCB bending. Pad cratering cracks are not detected by electrical testing or non-destructive inspection methods, yet they pose a long term reliability risk since the cracks may propagate under subsequent loads to cause electrical failure. Since the initiation of pad cratering does not result in an instantaneous electrical signature, detecting the onset of this failure has been challenging. An acoustic emission methodology was recently developed by the authors to detect the onset of pad cratering. The instantaneous release of elastic energy associated with the initiation of an internal crack, i.e., Acoustic Emission (AE), can be monitored to accurately determine the onset of both pad cratering and brittle intermetallic (IMC) failures.

Cisco Systems, Inc.

Can Age and Storage Conditions Affect the SIR Performance of a No-Clean Solder Paste Flux Residue?

Technical Library | 2017-02-09 17:08:44.0

The SMT assembly world, especially within the commercial electronics realm, is dominated by no-clean solder paste technology. A solder paste flux residue that does not require removal is very attractive in a competitive world where every penny of assembly cost counts. One important aspect of the reliability of assembled devices is the nature of the no-clean solder paste flux residue. Most people in this field understand the importance of having a process that renders the solder paste flux residue as benign and inert as possible, thereby ensuring electrical reliability.But, of all the factors that play into the electrical reliability of the solder paste flux residue, is there any impact made by the age of the solder paste and how it was stored? This paper uses J-STD-004B SIR (Surface Insulation Resistance) testing to examine this question.

Indium Corporation

Creep Corrosion Of Electronic Assemblies In Harsh Environments

Technical Library | 2022-03-16 19:41:17.0

Creep corrosion occurs in electronics assemblies and it is reminiscent to electromigration but does not require electrical field to drive the reaction. Corrosive elements and moisture must be present for creep corrosion to occur. Sulfur is the most prominent element to cause creep corrosion in environments such as paper mills, rubber manufacturing, mining, cement manufacturing, waste water treatment etc., also including companies and locations nearby such industries. The main part of printed circuit board assembly (PCBA) to be affected is the PCB surface finish. Especially immersion silver is prone to creep corrosion, but it sometimes occurs in NiPd (lead frames), and to a lesser extent in ENIG and OSP surface finishes. As the use of immersion silver is increasing as PCB surface finish and electronics are more and more used in harsh environments, creep corrosion is a growing risk. In this paper we will present the driving forces and mechanisms as well as suitable tests and mitigation strategies against creep corrosion

DfR Solutions

Effects of Flux and Reflow Parameters on Lead-Free Flip Chip Assembly

Technical Library | 2024-06-23 22:03:59.0

The melting temperatures of most lead-free solder alloys are somewhat higher than that of eutectic Sn/Pb solder, and many of the alloys tend to wet typical contact pads less readily. This tends to narrow down the fluxing and mass reflow process windows for assembly onto typical organic substrates and may enhance requirements on placement accuracy. Flip chip assembly here poses some unique challenges. The small dimensions provide for particular sensitivities to wetting and solder joint collapse, and underfilling does not reduce the demands on the intermetallic bond strength. Rather, the need to underfill lead to additional concerns in terms of underfill process control and reliability. Relatively little can here be learned from work on regular SMT components, BGAs or CSPs.

Binghamton University

Nondestructive Inspection of Underfill Layers Stacked up in Ceramics-Organics-Ceramics Packages with Scanning Acoustic Tomography (SAT)

Technical Library | 2017-06-15 00:44:19.0

Ceramics packages are being used in the electronics industry to operate the devices in harsh environments. In this paper we report a study on acoustic imaging technology for nondestructively inspecting underfill layers connecting organic interposers sandwiched between two ceramics substrates.First, we inspected the samples with transmission mode of scanning acoustic tomography (SAT) system, an inspection routine usually employed in assembly lines because of its simpler interpretation criteria: flawed region blocks the acoustic wave and appears darker. In this multilayer sample, this approach does not offer the crucial information at which layer of underfill has flaws. To resolve this issue, we use C-Mode Scanning in reflection mode to image layer by layer utilizing ultrasound frequencies from 15MHz to 120MHz. Although the sample is thick and contains at least 5 internal material interfaces, we are able to identify defective underfill layer interfaces.

Flex (Flextronics International)

The Compensation Problem and Solution Using Design of Experiments for Dense Multilayer Printed Circuit Boards

Technical Library | 2023-07-16 21:56:12.0

Imagine being able to accurately predict the correct artwork compensations prior to taking on a large quick turn order regardless of the board design, materials, or process. Such predictive power is possible and can be achieved without a lot of cost and complexity. This paper shows how small sets of designed experiments can be used to create a cImagine being able to accurately predict the correct artwork compensations prior to taking on a large quick turn order regardless of the board design, materials, or process. Such predictive power is possible and can be achieved without a lot of cost and complexity. This paper shows how small sets of designed experiments can be used to create a compensation model. Before a discussion of the design of experiments (DOEs), we will examine key processes and material variables that affect movement as demonstrated on real board design layout in a real production process. Only the few most relevant variables need to be included in the experimental design. A solution is presented that uses small experiments that provide the required information for constructing a general compensation model.mpensation model. Before a discussion of the design of experiments (DOEs), we will examine key processes and material variables that affect movement as demonstrated on real board design layout in a real production process. Only the few most relevant variables need to be included in the experimental design. A solution is presented that uses small experiments that provide the required information for constructing a general compensation model.

Isola Group


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