Technical Library | 2021-05-20 13:45:49.0
Manufacturers test to ensure that the product is built correctly. Shorts, opens, wrong or incorrectly inserted components, even catastrophically faulty components need to be flagged, found and repaired. When all such faults are removed, however, functional faults may still exist at normal operating speed, or even at lower speeds. Functional board test (FBT) is still required, a process that still relies on test engineers' understanding of circuit functionality and manually developed test procedures. While functional automatic test equipment (ATE) has been reduced considerably in price, FBT test costs have not been arrested. In fact, FBT is a huge undertaking that can take several weeks or months of test engineering development, unacceptably stretching time to market. The alternative, of selling products that have not undergone comprehensive FBT is equally, if not more, intolerable.
Technical Library | 2021-12-16 01:48:41.0
Package-on-Package (PoP) technology is widely used in mobile devices due to its simple design, lower cost and faster time to market. Warpage characteristic and requirement of PoP package becomes critical to ensure both the top and bottom package can be mounted with minimal yield lost. With this challenge in placed, iNEMI has been working relentlessly to fingerprint the current PoP package technology warpage characteristic and to establish some key learning for packaging technologies. The work also extended to understand the basic requirement needed for successful PoP stacking by analyzing the warpage data obtained and formulate a simple analytical equation to explain the true warpage requirement for PoP packaging.
Technical Library | 2007-03-13 14:28:27.0
This article tells what your electronic manufacturing service providers needs from you to prepare an accurate quotation for a typical printed circuit board assembly project.
Technical Library | 2007-03-13 14:32:40.0
This article outlines the minimum tasks needed to send your new electronic product idea out for prototyping. It lists and defines the minimums to either perform your self or to have subcontracted.
Technical Library | 2021-06-21 19:34:02.0
In this era of electronics miniaturization, high yield and low-cost integrated circuit (IC) substrates play a crucial role by providing a reliable method of high density interconnection of chip to board. In order to maximize substrate real-estate, the distance between Cu traces also known as line and space (L/S) should be minimized. Typical PCB technology consists of L/S larger than 40 µ whereas more advanced wafer level technology currently sits at or around 2 µm L/S. In the past decade, the chip size has decreased significantly along with the L/S on the substrate. The decreasing chip scales and smaller L/S distances has created unique challenges for both printed circuit board (PCB) industry and the semiconductor industry. Fan-out panel-level packaging (FOPLP) is a new manufacturing technology that seeks to bring the PCB world and IC/semiconductor world even closer. While FOPLP is still an emerging technology, the amount of high-volume production in this market space provide a financial incentive to develop innovative solutions in order to enable its ramp up. The most important performance aspect of the fine line plating in this market space is plating uniformity or planarity. Plating uniformity, trace/via top planarity, which measures how flat the top of the traces and vias are a few major features. This is especially important in multilayer processing, as nonuniformity on a lower layer can be transferred to successive layers, disrupting the device design with catastrophic consequences such as short circuits. Additionally, a non-planar surface could also result in signal transmission loss by distortion of the connecting points, like vias and traces. Therefore, plating solutions that provide a uniform, planar profile without any special post treatment are quite desirable.
Technical Library | 2023-06-02 17:37:43.0
This presentation of Nano Dimension Ltd. (the"Company") contains "forward-looking statements" within the meaning of the Private Securities Litigation Reform Act and other securities laws. Words such as "expects," "anticipates, " "intends, " "plans, " "believes, " "seeks, " "estimates" and similar expressions or variations of such words are intended to identify forward-looking statements. For example, the Company is using forward-looking statements when it discuss the potential of its products, strategic growth plan, its business plan and investment plans, the size fits addressable market, market growth, and expected recurring revenue growth. Forward-looking statements are no historical facts, and are based upon management's current expectations, beliefs and projections, many of which, by their nature, are inherently uncertain. Such expectations, beliefs and projections are expressed in good faith. However, there can be assurance that management's expectations, beliefs and projections will be achieved, and actual results may differ materially from what is expressed in or indicated by the forward-looking statements. Forward-looking statements are subject to risks and uncertainties that could cause actual performance or results to differ materially from those expressed in the forward-looking statements. For a more detailed description of the risks and uncertainties affecting the Company, reference is made to the Company's reports filed from time to time with the Securities and Exchange Commission ("SEC"), including, but not limited to, the risks detailed in the Company's annual report for the year ended December 31st, 2020, filed with the SEC. Forward-looking statements speak only as of the date the statements are made. The Company assumes no obligation to update forward-looking statements to reflect actual results, subsequent events or circumstances, changes in assumptions or changes in other factors affecting forward-looking information except to the extent required by applicable securities laws. If the Company does update one or more forward-looking statements, no inference should be drawn that the Company will make additional updates with respect thereto or with respect to other forward-looking statements.
Technical Library | 2019-04-10 22:08:31.0
The stimulating impact of the automotive industry has sharpened focus on immersion tin (i-Sn) more than ever before. Immersion tin with its associated attributes, is well placed to fulfill the requirements of such a demanding application. In an environment dominated by reliability, the automotive market not only has very stringent specifications but also demands thorough qualification protocols. Qualification is ultimately a costly exercise. The good news is that i-Sn is already qualified by many tier one OSATs. The focus of this paper is to generate awareness of the key factors attributed to soldering i-Sn. Immersion tin is not suitable for wire bonding but ultimately suited for multiple soldering applications. The dominant topics of this paper will be IMC formations in relation to reflow cycles and the associated solderability performance. Under contamination free conditions, i-Sn can provide a solderable finish even after multiple reflow cycles. The reflow conditions employed in this paper are typical for lead free soldering environments and the i-Sn thicknesses are approximately 1 μm.
Technical Library | 2017-04-20 13:51:14.0
The one constant in electronics manufacturing is change. Moore's Law, which successfully predicted a rate of change at which transistor counts doubled on Integrated Circuits (ICs) at lower cost for decades, is ceding to be an appropriate prediction tool. Increasing technical and economic requirements, deriving from the semiconductor environment, are cascaded down to the printed circuit and in particular to the IC substrate manufacturers. This is both a challenge and an opportunity for IC Substrate manufacturers, when dealing with the demands of the packaging market. (...)This paper introduces two new electroless copper baths developed for IC substrates manufacturing based on Semi Additive Process (SAP) technology (hereafter referred to as E'less Copper IC) and HDI production (hereafter referred to as E'less Copper HDI) and optimized for high throw into BMVs. An introduction to reliable throwing power measurement methods based on scanning electron microscope (SEM) is given, followed by a compilation and discussion of key performance criteria for each application, namely throwing power, copper adhesion on the substrate, dry film adhesion and reliability.
Technical Library | 2018-01-04 11:05:34.0
Traceability has grown from being a specialized need for certain safety critical segments of the industry, to now being a recognized value-add tool for the industry as a whole. The perception of traceability data collection however persists as being a burden that may provide value only when the most rare and disastrous of events take place. Disparate standards have evolved in the industry, mainly dictated by large OEM companies in the market create confusion, as a multitude of requirements and definitions proliferate. The intent of the IPC-1782 project is to bring the whole principle and perception of traceability up to date. Traceability, as defined in this standard will represent the most effective quality tool available, becoming an intrinsic part of best practice operations, with the encouragement of automated data collection from existing manufacturing systems, integrating quality, reliability, predictive (routine, preventative, and corrective) maintenance, throughput, manufacturing, engineering and supply-chain data, reducing cost of ownership as well as ensuring timeliness and accuracy all the way from a finished product back through to the initial materials and granular attributes about the processes along the way.
Technical Library | 2021-04-08 00:30:49.0
As the electronic industry moves to lead-free assembly and finer-pitch circuits, widely used printed wiring board (PWB) finish, SnPb HASL, has been replaced with lead-free and coplanar PWB finishes such as OSP, ImAg, ENIG, and ImSn. While SnPb HASL offers excellent corrosion protection of the underlying copper due to its thick coating and inherent corrosion resistance, the lead-free board finishes provide reduced corrosion protection to the underlying copper due to their very thin coating. For ImAg, the coating material itself can also corrode in more aggressive environments. This is an issue for products deployed in environments with high levels of sulfur containing pollutants encountered in the current global market. In those corrosive environments, creep corrosion has been observed and led to product failures in very short service life (1-5 years). Creep corrosion failures within one year of product deployment have also been reported. This has prompted an industry-wide effort to understand creep corrosion
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