Technical Library | 2024-04-08 15:46:36.0
A designed experiment evaluated the influence of several variables on appearance and strength of Pb-free solder joints. Components, with leads finished with nickel-palladium-gold (NiPdAu), were used from Texas Instruments (TI) and two other integrated circuit suppliers. Pb-free solder paste used was tin-silver-copper (SnAgCu) alloy. Variables were printed wiring board (PWB) pad size/stencil aperture (the pad finish was consistent; electrolysis Ni/immersion Au), reflow atmosphere, reflow temperature, Pd thickness in the NiPdAu finish, and thermal aging. Height of solder wetting to component lead sides was measured for both ceramic plate and PWB soldering. A third response was solder joint strength; a "lead pull" test determined the maximum force needed to pull the component lead from the PWB. This paper presents a statistical analysis of the designed experiment. Reflow atmosphere and pad size/stencil aperture have the greatest contribution to the height of lead side wetting. Reflow temperature, palladium thickness, and preconditioning had very little impact on side-wetting height. For lead pull, variance in the data was relatively small and the factors tested had little impact.
Technical Library | 2020-08-27 01:22:45.0
Initially adopted internal specifications for acceptance of printed circuit boards (PCBs) used for wire bonding was that there were no nodules or scratches allowed on the wirebond pads when inspected under 20X magnification. The nodules and scratches were not defined by measurable dimensions and were considered to be unacceptable if there was any sign of a visual blemish on wire-bondable features. Analysis of the yield at a PCB manufacturer monitored monthly for over two years indicated that the target yield could not be achieved, and the main reasons for yield loss were due to nodules and scratches on the wirebonding pads. The PCB manufacturer attempted to eliminate nodules and scratches. First, a light-scrubbing step was added after electroless copper plating to remove any co-deposited fine particles that acted as a seed for nodules at the time of copper plating. Then, the electrolytic copper plating tank was emptied, fully cleaned, and filtered to eliminate the possibility of co-deposited particles in the electroplating process. Both actions greatly reduced the density of the nodules but did not fully eliminate them. Even though there was only one nodule on any wire-bonding pad, the board was still considered a reject. To reduce scratches on wirebonding pads, the PCB manufacturer utilized foam trays after routing the boards so that they did not make direct contact with other boards. This action significantly reduced the scratches on wire-bonding pads, even though some isolated scratches still appeared from time to time, which caused the boards to be rejected. Even with these significant improvements, the target yield remained unachievable. Another approach was then taken to consider if wire bonding could be successfully performed over nodules and scratches and if there was a dimensional threshold where wire bonding could be successful. A gold ball bonding process called either stand-off-stitch bonding (SSB) or ball-stitch-on-ball bonding (BSOB) was used to determine the effects of nodules and scratches on wire bonds. The dimension of nodules, including height, and the size of scratches, including width, were measured before wire bonding. Wire bonding was then performed directly on various sizes of nodules and scratches on the bonding pad, and the evaluation of wire bonds was conducted using wire pull tests before and after reliability testing. Based on the results of the wire-bonding evaluation, the internal specification for nodules and scratches for wirebondable PCBs was modified to allow nodules and scratches with a certain height and a width limitation compared to initially adopted internal specifications of no nodules and no scratches. Such an approach resulted in improved yield at the PCB manufacturer.
Technical Library | 2024-04-29 21:39:52.0
In this paper, we develop and put into practice an Automatic Optical Inspection (AOI) system based on machine vision to check the holes on a printed circuit board (PCB). We incorporate the hardware and software. For the hardware part, we combine a PC, the three-axis positioning system, a lighting device and CCD cameras. For the software part, we utilize image registration, image segmentation, drill numbering, drill contrast, and defect displays to achieve this system. Results indicated that an accuracy of 5µm could be achieved in errors of the PCB holes allowing comparisons to be made. This is significant in inspecting the missing, the multi-hole and the incorrect location of the holes. However, previous work only focusses on one or other feature of the holes. Our research is able to assess multiple features: missing holes, incorrectly located holes and excessive holes. Equally, our results could be displayed as a bar chart and target plot. This has not been achieved before. These displays help users analyze the causes of errors and immediately correct the problems. Additionally, this AOI system is valuable for checking a large number of holes and finding out the defective ones on a PCB. Meanwhile, we apply a 0.1mm image resolution which is better than others used in industry. We set a detecting standard based on 2mm diameter of circles to diagnose the quality of the holes within 10 seconds.
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
Technical Library | 2019-09-11 23:33:04.0
There are numerous techniques to singulate printed circuit boards after assembly including break-out, routing, wheel cutting and now laser cutting. Lasers have several desirable advantages such as very narrow kerf widths as well as virtually no dust, no mechanical stress, visual pattern recognition and fast set-up changes. The very narrow kerf width resulting from laser ablation and the very tight tolerance of the cutting path placement allows for more usable space on the panel. However, the energy used in the laser cutting process can also create unwanted products on the cut walls as a result of the direct laser ablation. The question raised often is: What are these products, and how far can the creation of such products be mitigated through variation of the laser cutting process, laser parameters and material handling? This paper discusses the type and quantity of the products found on sidewalls of laser depaneled circuit boards and it quantifies the results through measurements of breakdown voltage, as well as electrical impedance. Further this paper discusses mitigation strategies to prevent or limit the amount of change in surface quality as a result of the laser cutting process. Depending on the final application of the circuit board it may prompt a need for proper specification of the expected results in terms of cut surface quality. This in turn will impact the placement of runs and components during layout. It will assist designers and engineers in defining these parameters sufficiently in order to have a predictable quality of the circuit boards after depaneling.
Technical Library | 2020-10-08 00:55:22.0
This article presents the development of a stretchable sensor network with high signal-to-noise ratio and measurement accuracy for real-time distributed sensing and remote monitoring. The described sensor network was designed as an island-and-serpentine type network comprising a grid of sensor "islands" connected by interconnecting "serpentines." A novel high-yield manufacturing process was developed to fabricate networks on recyclable 4-inch wafers at a low cost. The resulting stretched sensor network has 17 distributed and functionalized sensing nodes with low tolerance and high resolution. The sensor network includes Piezoelectric (PZT), Strain Gauge(SG), and Resistive Temperature Detector (RTD) sensors. The design and development of a flexible frame with signal conditioning, data acquisition, and wireless data transmission electronics for the stretchable sensor network are also presented. The primary purpose of the frame subsystem is to convert sensor signals into meaningful data, which are displayed in real-time for an end-user to view and analyze. The challenges and demonstrated successes in developing this new system are demonstrated, including (a) developing separate signal conditioning circuitry and components for all three sensor types (b) enabling simultaneous sampling for PZT sensors for impact detection and (c)configuration of firmware/software for correct system operation. The network was expanded with an in-house developed automated stretch machine to expand it to cover the desired area. The released and stretched network was laminated into an aerospace composite wing with edge-mount electronics for signal conditioning, processing, power, and wireless communication.
Technical Library | 2020-10-14 14:33:36.0
Epoxy based adhesives are prevalent interface materials for all levels of electronic packaging. One reason for their widespread success is their ability to accept fillers. Fillers allow the adhesive formulator to tailor the electrical and thermal properties of a given epoxy. Silver flake allow the adhesive to be both electrically conductive and thermally conductive. For potting applications, heat sinking, and general encapsulation where high electrical isolation is required, aluminum oxide has been the filler of choice. Today, advanced Boron Nitride filled epoxies challenge alternative thermal interface materials like silicones, greases, tapes, or pads. The paper discusses key attributes for designing and formulating advanced thermally conductive epoxies. Comparisons to other common fillers used in packaging are made. The filler size, shape and distribution, as well as concentration in the resin, will determine the adhesive viscosity and rheology. Correlation's between Thermal Resistance calculations and adhesive viscosity are made. Examples are shown that determination of thermal conductivity values in "bulk" form, do not translate into actual package thermal resistance. Four commercially available thermally conductive adhesives were obtained for the study. Adhesives were screened by shear strength measurements, Thermal Cycling ( -55 °C to 125 °C ) Resistance, and damp heat ( 85 °C / 85 %RH ) resistance. The results indicate that low modulus Boron Nitride filled epoxies are superior in formulation and design. Careful selection of stress relief agents, filler morphology, and concentration levels are critical choices the skilled formulator must make. The advantages and limitations of each are discussed and demonstrated.
Technical Library | 2023-04-17 17:05:47.0
In an ideal world, manufacturing devices would work all of the time, however, every company receives customer returns for a variety of reasons. If these returned parts contributed to a fail, most companies will perform failure analysis (FA) on the returned parts to determine the root cause of the failure. Failure can occur for a multitude of reasons, for example: wear out, fatigue, design issues, manufacturing flaw or defect. This information is then used to improve the overall quality of the product and prevent reoccurrence. If no defect is found, it is possible that in fact the product has no defect. On the other hand, the defect could be elusive and the FA techniques insufficient to detect said deficiency. No-clean flux residues can cause intermittent or elusive, hard to find defects. In an attempt to understand the effects of no-clean flux residues from the secondary soldering and cleaning processes, a matrix of varying process and cleaning operation was investigated. Of special interest, traveling flux residues and entrapped residues were examined, as well as localized and batch cleaning processes. Various techniques were employed to test the remaining residues in order to assess their propensity to cause a latent failure. These techniques include Surface Insulation Resistance1 (SIR) testing at 40⁰C/90% RH, 5 VDC bias along with C32 testing and Ion Exchange Chromatography (IC). These techniques facilitate the assessment of the capillary effect the tight spacing these component structures have when flux residues are present. It is expected that dendritic shorting and measurable current leakage will occur, indicating a failing SIR test. However, since the residue resides under the discrete components, there will be no visual evidence of dendritic growth or metal migration.
Technical Library | 2023-06-02 14:13:02.0
This work examines the use of dual-material fused filament fabrication for 3D printing electronic componentsand circuits with conductive thermoplastic filaments. The resistivity of traces printed fromconductive thermoplastic filaments made with carbon-black, graphene, and copper as conductive fillerswas found to be 12, 0.78, and 0.014 ohm cm, respectively, enabling the creation of resistors with valuesspanning 3 orders of magnitude. The carbon black and graphene filaments were brittle and fracturedeasily, but the copper-based filament could be bent at least 500 times with little change in its resistance.Impedance measurements made on the thermoplastic filaments demonstrate that the copper-based filamenthad an impedance similar to a copper PCB trace at frequencies greater than 1 MHz. Dual material3D printing was used to fabricate a variety of inductors and capacitors with properties that could bepredictably tuned by modifying either the geometry of the components, or the materials used to fabricatethe components. These resistors, capacitors, and inductors were combined to create a fully 3Dprinted high-pass filter with properties comparable to its conventional counterparts. The relatively lowimpedance of the copper-based filament enabled its use for 3D printing of a receiver coil for wirelesspower transfer. We also demonstrate the ability to embed and connect surface mounted components in3D printed objects with a low-cost ($1000 in parts), open source dual-material 3D printer. This work thusdemonstrates the potential for FFF 3D printing to create complex, three-dimensional circuits composedof either embedded or fully-printed electronic components.
Technical Library | 2018-10-18 15:41:45.0
One specific market space of interest to emerging printed electronics is In Mold Label (IML) technology. IML is used in many consumer products and white good applications. When combined with electronics, the In Mold Electronics (IME) adds compelling new product functionality. Many of these products have multi-dimensional features and therefore require thermoforming processes in order to prepare the labels before they are in-molded. While thermoforming is not a novel technique for IML, the addition of printed electronic functional traces is not well documented. There is little or no published work on printed circuit performance and design interactions in the thermoforming process that could inform improved IME product designs. A general full factorial Design of Experiments (DOE) was used to analyze the electrical performance of the conductive silver ink trace/polycarbonate substrate system. Variables of interest include trace width, height of draw, and radii of both top and bottom curvatures in the draw area. Thermoforming tooling inserts were fabricated for eight treatment combinations of these variables. Each sample has one control and two formed strips. Electrical measurements were taken of the printed traces on the polymer sheets pre- and post- forming with a custom fixture to evaluate the effect on resistance. The design parameters found to be significant were draw height and bottom radius, with increased draw and smaller bottom curvature radii both contributing to the circuits’ resistance degradation. Over the ranges evaluated, the top curvature radii had no effect on circuit resistance. Interactions were present, demonstrating that circuit and thermoforming design parameters need to be studied as a system. While significant insight impacting product development was captured further work will be executed to evaluate different ink and substrate material sets, process variables, and their role in IME.
