Technical Library | 2017-12-11 22:31:06.0
Typical printed circuit board assemblies (PCBAs) processed by reflow, wave, or selective wave soldering were analysed for typical levels of process related residues, resulting from a specific or combination of soldering process. Typical solder flux residue distribution pattern, composition, and concentration are profiled and reported. Presence of localized flux residues were visualized using a commercial Residue RAT gel test and chemical structure was identified by FT-IR, while the concentration was measured using ion chromatography, and the electrical properties of the extracts were determined by measuring the leak current using a twin platinum electrode setup. Localized extraction of residue was carried out using a commercial C3 extraction system. Results clearly show that the amount and distribution of flux residues are a function of the soldering process, and the level can be reduced by an appropriate cleaning. Selective soldering process generates significantly higher levels of residues compared to the wave and reflow process. For conformal coated PCBAs, the contamination levels generated from the tested wave and selective soldering process are found to be enough to generate blisters under exposure to high humidity levels.
Technical Library | 2020-05-07 03:46:27.0
The selective soldering process has evolved to become a standard production process within the electronics assembly industry, and now accommodates a wide variety of through-hole component formats in numerous applications. Most through-hole components can be easily soldered with the selective soldering process without difficulty, however some types of challenging components require additional attention to ensure optimum quality control is maintained. Several high thermal mass components can place demands on the selective soldering process, while the use of specialized solder fixtures and/or pallets often places an additional thermal demand on the preheating process. Fine-pitch through-hole components and connectors place a different set of demands on the selective soldering process and typically require special attention to lead projection and traverse speed to minimize bridging between adjacent pins. Dual in-line memory module (DIMM) connectors, compact peripheral component interface (cPCI) connectors, coax connectors and other high thermal mass components as well as fine-pitch microconnectors,can present challenges when soldered into backplanes or multilayer printed circuit board assemblies. Adding to this challenge, compact peripheral component interface connectors can present additional solderability issues due to their beryllium copper termination pins.
Technical Library | 2023-07-25 16:42:54.0
Printing solder paste for very small components like .3mm pitch CSP's and 01005 Chip Components is a challenge for the printing process when other larger components like RF shields, SMT Connectors, and large chip or resistor components are also present on the PCB. The smaller components require a stencil thickness typically of 3 mils (75u) to keep the Area Ratio greater than .55 for good paste transfer efficiency. The larger components require either more solder paste height or volume, thus a stencil thickness in the range of 4 to 5 mils (100 to 125u). This paper will explore two stencil solutions to solve this dilemma. The first is a "Two Print Stencil" option where the small component apertures are printed with a thin stencil and the larger components with a thicker stencil with relief pockets for the first print. Successful prints with Keep-Outs as small as 15 mils (400u) will be demonstrated. The second solution is a stencil technology that will provide good paste transfer efficiency for Area Ratio's below .5. In this case a thicker stencil can be utilized to print all components. Paste transfer results for several different stencil types including Laser-Cut Fine Grain stainless steel, Laser-Cut stainless steel with and w/o PTFE Teflon coating, AMTX E-FAB with and w/o PTFE coating for Area Ratios ranging from .4 up to .69.
Technical Library | 2019-09-11 23:33:04.0
There are numerous techniques to singulate printed circuit boards after assembly including break-out, routing, wheel cutting and now laser cutting. Lasers have several desirable advantages such as very narrow kerf widths as well as virtually no dust, no mechanical stress, visual pattern recognition and fast set-up changes. The very narrow kerf width resulting from laser ablation and the very tight tolerance of the cutting path placement allows for more usable space on the panel. However, the energy used in the laser cutting process can also create unwanted products on the cut walls as a result of the direct laser ablation. The question raised often is: What are these products, and how far can the creation of such products be mitigated through variation of the laser cutting process, laser parameters and material handling? This paper discusses the type and quantity of the products found on sidewalls of laser depaneled circuit boards and it quantifies the results through measurements of breakdown voltage, as well as electrical impedance. Further this paper discusses mitigation strategies to prevent or limit the amount of change in surface quality as a result of the laser cutting process. Depending on the final application of the circuit board it may prompt a need for proper specification of the expected results in terms of cut surface quality. This in turn will impact the placement of runs and components during layout. It will assist designers and engineers in defining these parameters sufficiently in order to have a predictable quality of the circuit boards after depaneling.
Technical Library | 2023-04-17 21:17:59.0
The purpose of this paper is to evaluate and compare the effectiveness and sensitivity of different cleanliness verification tests for post soldered printed circuit board assemblies (PCBAs) to provide an understanding of current industry practice for ionic contamination detection limits. Design/methodology/approach – PCBAs were subjected to different flux residue cleaning dwell times and cleanliness levels were verified with resistivity of solvent extract, critical cleanliness control (C3) test, and ion chromatography analyses to provide results capable of differentiating different sensitivity levels for each test. Findings – This study provides an understanding of current industry practice for ionic contamination detection using verification tests with different detection sensitivity levels. Some of the available cleanliness monitoring systems, particularly at critical areas of circuitry that are prone to product failure and residue entrapment, may have been overlooked. Research limitations/implications – Only Sn/Pb, clean type flux residue was evaluated. Thus, the current study was not an all encompassing project that is representative of other chemistry-based flux residues. Practical implications – The paper provides a reference that can be used to determine the most suitable and effective verification test for the detection of ionic contamination on PCBAs. Originality/value – Flux residue-related problems have long existed in the industry. The findings presented in this paper give a basic understanding to PCBA manufacturers when they are trying to choose the most suitable and effective verification test for the detection of ionic contamination on their products. Hence, the negative impact of flux residue on the respective product's long-term reliability and performance can be minimized and monitored effectively.
