Technical Library | 2019-08-19 09:46:13.0
Boundary scan is a method for testing interconnects on printed circuit boards (PCBs) or sub-blocks inside an integrated circuit. It has rapidly become the technology of choice for building reliable high technology electronic products with a high degree of testability. Due to the low-cost and integrated circuit (IC) level access capabilities of boundary scan, its use has expanded beyond traditional board test applications into product design and service.
Technical Library | 2019-06-07 14:49:54.0
ACI Technologies was contacted in regards to poor solder joint reliability. The customer submitted an assembly that was exhibiting intermittent opens at multiple locations on a ball grid array (BGA) component. The assembly’s functionality did not survive international shipping, essentially shock and vibration failures, immediately making the quality of the solder joints suspect. The customer was asked about the contract manufacturer and the reflow oven profile as well as the solder paste and surface finish used. The ACI engineering staff evaluated the contract manufacturer’s technique and determined that they were competent in the methods they used for placing thermocouples in the proper locations and developing the reflow oven profile. The surface finish was unusual, but not unheard of, in that it was hard gold over hard nickel, rather than electroless nickel immersion gold (ENIG). The customer was able to supply boundary scan testing data which showed a diagonal row of troublesome BGA pins.
Technical Library | 2018-07-25 21:37:11.0
This paper will discuss the expanded use of boundary-scan testing beyond the typical manufacturing test to capture structural defects on a component/devices in a printed circuit board assembly (PCBA). The following topics will be discussed to demonstrate the capability of boundary-scan test system on how we can extend beyond typical manufacturing test: Boundary-scan as a complete manufacturing test system, Boundary-scan implementation during PCBA design stage, Implementation of boundary-scan beyond typical structural testing
Technical Library | 2010-05-24 23:47:35.0
Die echte Integration zwischen ATE Flying Prober und Boundary Scan Tester, vorgestellt von Seica, kombiniert das Beste von beiden Testtechniken und multipliziert die Vorteile für den Anwender.
Technical Library | 2015-12-17 17:24:17.0
Product quality can be improved through proper application of design for test (DFT) strategies. With today's shrinking product sizes and increasing functionality, it is difficult to get good test coverage of loaded printed circuit boards due to the loss of test access. Advances in test techniques, such as boundary scan, help to recover this loss of test coverage. However, many of these test techniques need to be designed into the product to be effective.This paper will discuss how to maximize the benefits of boundary scan test, including specific examples of how designers should select the right component, connect multiple boundary scan components in chains, add test access to the boundary scan TAP ports, etc. A discussion of DFT guidelines for PCB layout designers is also included. Finally, this paper will include a description of some advanced test methods used in in-circuit tests, such as vectorless test and special probing methods, which are implemented to improve test coverage on printed circuit boards with limited test access.
Technical Library | 2013-02-14 12:54:29.0
Boundary-scan (1149.1) technology was originally developed to provide a far easier method to perform digital DC testing to detect intra-IC interconnect assembly faults, such as solder shorts and opens. Today's advanced IC technology now includes high-speed differential interfaces that include AC or DC coupling components loaded on the printed circuit assembly. Simple stuck-at-high/low test methods are not sufficient to detect all assembly fault conditions, which includes shorts, opens and missing components. Improved diagnostics requires detailed circuit analysis, predictive assembly fault simulation and more complex testing to isolate and accurately detect all possible assembly faults... First published in the 2012 IPC APEX EXPO technical conference proceedings
Technical Library | 2007-08-23 14:30:03.0
The complexity and programmability of modern embedded boards means that knowledge built up during debugging and testing must be regarded as Intellectual Property (IP) and therefore preserved. But many of the processes and tools used today do not provide a means to preserve or pass on this IP, and thereby forego valuable opportunities to save time and improve quality during subsequent stages of product development.
Technical Library | 2010-05-20 17:17:03.0
As several industry pundits have expressed in recent years: "the era of 'one test method fits all' seems well behind us." For most test managers with even a modest mix of products, trying to formulate a test policy/philosophy has become a tricky balancing act at the best of times. James Stanbridge, Sales Manager UK for JTAG Technologies, and Steve Lees Managing Director of ATE Solutions look at the options.
Technical Library | 2015-05-11 21:27:52.0
Originating from the last millenium, almost three decades ago, the introduction of surface mount packaging triggered a wave of changes throughout many aspects of electronics production. A small number of talented, innovative test engineers from various big players of the industry started to attend meetings to discuss the impact of that change of technology on their future test concepts for modern assemblies. The Joint Test Action Group was born.
Technical Library | 2018-08-01 11:25:59.0
With complexities of PCB design scaling and manufacturing processes adopting to environmentally friendly practices raise challenges in ensuring structural quality of PCBs. This makes it essential to have a good 'Design for Test' (DFT) to ensure a robust structural test. (...)During the course of the DFT review, can we realize a good test strategy for the PCBA. How can the test strategy of the PCBA be partitioned as to what portions of the design can be covered structurally and what is covered functionally, in a way that provides best diagnostics to discover faults
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