Technical Library | 2023-01-17 17:27:13.0
Reflow profile has significant impact on solder joint performance because it influences wetting and microstructure of the solder joint. The degree of wetting, the microstructure (in particular the intermetallic layer), and the inherent strength of the solder all factor into the reliability of the solder joint. This paper presents experimental results on the effect of reflow profile on both 63%Sn 37%Pb (SnPb) and 96.5%Sn 3.0%Ag 0.5%Cu (SAC 305) solder joint shear force. Specifically, the effect of the reflow peak temperature and time above solder liquidus temperature are studied. Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb have been developed with three levels of peak temperature (230 o C, 240 o C, and 250 o C for SAC 305; and 195 o C, 205 o C, and 215 o C for SnPb) and three levels of time above solder liquidus temperature (30 sec., 60 sec., and 90 sec.). The shear force data of four different sizes of chip resistors (1206, 0805, 0603, and 0402) are compared across the different profiles. The shear force of the resistors is measured at time 0 (right after assembly). The fracture surfaces have been studied using a scanning electron microscopy (SEM) with energy dispersive spectroscopy (EDS)
Technical Library | 2023-01-17 17:19:44.0
A test program was developed to evaluate the effectiveness of vacuum reflow processing on solder joint voiding and subsequent thermal cycling performance. Area array package test vehicles were assembled using conventional reflow processing and a solder paste that generated substantial void content in the solder joints. Half of the population of test vehicles then were re-processed (reflowed) using vacuum reflow. Transmission x-ray inspection showed a significant reduction in solder voiding after vacuum processing. The solder attachment reliability of the conventional and vacuum reflowed test vehicles was characterized and compared using two different accelerated thermal cycling profiles. The thermal cycling results are discussed in terms of the general impact of voiding on solder thermal fatigue reliability, results from the open literature, and the evolving industry standards for solder voiding. Recommendations are made for further work based on other void reduction methods and additional reliability studies.
Technical Library | 2023-01-17 17:22:28.0
The impact of voiding on the solder joint integrity of ball grid arrays (BGAs)/chip scale packages (CSPs) can be a topic of lengthy and energetic discussion. Detailed industry investigations have shown that voids have little effect on solder joint integrity unless they fall into specific location/geometry configurations. These investigations have focused on thermal cycle testing at 0°C-100°C, which is typically used to evaluate commercial electronic products. This paper documents an investigation to determine the impact of voids in BGA and CSP components using thermal cycle testing (-55°C to +125°C) in accordance with the IPC- 9701 specification for tin/lead solder alloys. This temperature range is more typical of military and other high performance product use environments. A proposed BGA void requirement revision for the IPC-JSTD-001 specification will be extracted from the results analysis.
Technical Library | 2023-01-17 17:12:33.0
Reflowed indium metal has for decades been the standard for solder thermal interface materials (solder TIMs or sTIMs) in most high-performance computing (HPC) TIM1 applications. The IEEE Heterogeneous Integration Thermal roadmap states that new thermal interface materials solutions must provide a path to the successful application of increased total-package die areas up to 100cm2. While GPU architectures are relatively isothermal during usage, CPU hotspots in complex heterogeneously-integrated modules will need to be able to handle heat flux hotspots up to 1000W/cm2 within the next two years. Indium and its alloys are used as reflowed solder thermal interface materials in both CPU and GPU "die to lid/heat spreader" (TIM1) applications. Their high bulk thermal conductivity and proven long-term reliability suit them well for extreme thermomechanical stresses. Voiding is the most important failure mode and has been studied by x-ray. The effects of surface pretreatment, pressure during reflow, solder flux type/fluxless processing, and preform design parameters, such as alloy type, are also examined. The paper includes data on both vacuum and pressure (autoclave) reflow of sTIMs, which is becoming necessary to meet upcoming requirements for ultralow voiding in some instances.
Technical Library | 2019-06-21 10:39:15.0
Recently, an ACI Technologies (ACI) customer called to discuss failures that they had observed with some through-hole capacitor parts. The components were experiencing failures following vibration and accelerated stress testing. Upon receipt of the samples, ACI performed three levels of inspection and Energy Dispersive Spectroscopy (EDS) testing to investigate the root cause of the failures. These analyses enabled ACI to verify the elements comprising the solder joints and make the following recommendations in order to prevent future occurrences. The first inspection was to investigate the capacitor leads using optical microscopy, and no anomalies were found that could indicate bad parts from the vendor or improper handling prior to assembly. However, vertical fill in the barrel of the plated through-holes was too close to the IPC-A-610 minimum specification of 75% to determine a pass/fail condition, and therefore required further investigation.
Technical Library | 2023-09-16 06:27:24.0
Vacuum reflow ovens are the best way to solder SMD components. They create a controlled environment that prevents oxidation and improves solder joint quality.
Technical Library | 2019-09-03 17:06:09.0
Both optical and scanning electron microscopy (SEM) are powerful tools for failure analysis in electronics and are used for low and high magnification examination. This article will provide detailed, step by step information for examining solder joints.
Technical Library | 2019-05-21 17:20:36.0
Die attach material selection and process implementation play crucial roles in any microelectronic assembly. The chosen attach methods ultimately affect die stress, functionality, thermal management, and reliability of the assembly. Die attach applications are designed to optimize mechanical attachment of the die to the substrate, to create a thermal path from the die to the substrate, and to create an electrical path for a ground plane connection. Some of the more commonly used die attach materials in the microelectronics industry today are epoxies,polyimides, thermoplastics, silicones, solders, and special low outgassing, low stress, anisotropic adhesives.
Technical Library | 2019-06-20 07:45:19.0
One of the two basic risks of employing the commercially accepted, Restriction of Hazardous Substances (RoHS) compliant, lead-free (Pb-free) electronics is the threat to the electronics reliability from the growth of tin whiskers. The other basic risk deals with Pb-free solder joint reliability.
Technical Library | 2019-06-07 14:49:54.0
ACI Technologies was contacted in regards to poor solder joint reliability. The customer submitted an assembly that was exhibiting intermittent opens at multiple locations on a ball grid array (BGA) component. The assembly’s functionality did not survive international shipping, essentially shock and vibration failures, immediately making the quality of the solder joints suspect. The customer was asked about the contract manufacturer and the reflow oven profile as well as the solder paste and surface finish used. The ACI engineering staff evaluated the contract manufacturer’s technique and determined that they were competent in the methods they used for placing thermocouples in the proper locations and developing the reflow oven profile. The surface finish was unusual, but not unheard of, in that it was hard gold over hard nickel, rather than electroless nickel immersion gold (ENIG). The customer was able to supply boundary scan testing data which showed a diagonal row of troublesome BGA pins.
