Electronics Forum: chips (Page 109 of 260)

Is there some general file format for chip placement on pcb

Electronics Forum | Mon Nov 17 08:01:44 EST 2003 | stefwitt

The format is X,Y Theta of the component center for all placement machines. Gerber data can be useless, unless you have the reference from pin 1 to the component center. Some machines offer a CAD convertion tool. I don't know any machine, which can

Ceramic Chip Cap Processing

Electronics Forum | Wed Nov 19 16:28:22 EST 2003 | davef

A nearby company specifies 'no wave soldering of second side SMT components' [er, words to that effect] to their CM. Among the the previous threads on SMTnet are: http://www.smtnet.com/forums/Index.cfm?CFApp=1&Message_ID=16944 http://www.smtnet.c

need all

Electronics Forum | Sat Dec 13 16:13:19 EST 2003 | adlsmt

After you get your prices, list the stuff here and get some performance, rather than price feedback on what you are looking to buy. Consider what you need to place and make sure the equipment matches it. If your doing 16mil T-Sops you wont be happy w

PC Assembly of 0.5mm pitch array Chip Scale Package with HASL fi

Electronics Forum | Thu Dec 18 23:44:53 EST 2003 | Dean

...don't expect high yields with hasl on that device. Yeah, you an do it. But not reliably. Also, factor in board warp, bump tolerance AND HASL variation....recipe for disaster. can your process toleate a selective gold on the one device? How ab

voids- leaded and chip components

Electronics Forum | Fri Jan 23 10:39:35 EST 2004 | patrickbruneel

Kris, I assume with voids you mean acceptable solder coverage of pad and lead. As Dave mentioned I also have not seen any specific studies on voids, but workman ship standards exist about acceptable coverage of pad and lead (both consumer and MIL)

Chip Components with big ground pads - Unsolder

Electronics Forum | Mon Jan 26 21:10:36 EST 2004 | Vinny

I have done acurate profiling which meets the solder paste specifications. The point I am trying to highlight here is also due to the ground plane side being much larger causing the tombstone defect. I have even tried doing a linear profile, it hel

Chip Components with big ground pads - Unsolder

Electronics Forum | Wed Jan 28 20:58:16 EST 2004 | davef

Vinny: From a thermal standpoint, your choices are: * Get your customer to design thermal relief in the board. * Set your thermal recipe to assure that the grounded pad reaches reflow temperature. This may require a long soak at a single temperature

LGA design

Electronics Forum | Thu Feb 12 21:06:20 EST 2004 | davef

"LGA" [land grid array] is a pretty broad topic. Search the fine SMTnet Archives for background on: * BGA * uBGA * Flip chip * etc Consider: * Area Array Packaging Handbook: Manufacturing and Assembly; Ken Gilleo; McGraw-Hill Professional; 1st edit

qfp reflow problems

Electronics Forum | Thu Apr 22 12:27:47 EDT 2004 | barry

I placed thermo's at 2 of the problem devices. Soak (time 150 to 180) 100 sec. Time above 180 =80 secs with 208 deg. peak. The solder appeared to flow at these pads, but little to no adhesion to the joint.Total time in oven was 5 min. All other joint

Cleaning of stencil

Electronics Forum | Thu Apr 22 12:46:41 EDT 2004 | Mark

What type of chip bonder you use? I use Loctite 3611... part #25410 on my stencil screening and use epoxy cleaner, air hose and that takes care of our issues. If you use alchol it just hardens the epoxy so make sure its cleaned out good before restor


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