Used SMT Equipment | In-Circuit Testers
Agilent-Keysight 8904A Multifunction Synthesizer The 8904A Multifunction Synthesizer uses the latest VSLIC technology to create complex signals from six fundamental waveforms. The unit digitally synthesizes precise sine, square, triangle, ramp,
Used SMT Equipment | In-Circuit Testers
Agilent-Keysight 8904A Multifunction Synthesizer The 8904A Multifunction Synthesizer uses the latest VSLIC technology to create complex signals from six fundamental waveforms. The unit digitally synthesizes precise sine, square, triangle, ramp,
Designed for testing large and complex PCBAs, the TR8100LV is TRI’s top-of-the-line board test system targeting the low-voltage testing market. TR8100LV’s vacuum system ensures full pin contact and with up to 3,584 pin digital MUX-free architecture,
Technical Library | 2020-07-08 20:05:59.0
There is a compelling need for functional testing of high-speed input/output signals on circuit boards ranging from 1 gigabit per second (Gbps) to several hundred Gbps. While manufacturing tests such as Automatic Optical Inspection (AOI) and In-Circuit Test (ICT) are useful in identifying catastrophic defects, most high-speed signals require more scrutiny for failure modes that arise due to high-speed conditions, such as jitter. Functional ATE is seldom fast enough to measure high-speed signals and interpret results automatically. Additionally, to measure these adverse effects it is necessary to have the tester connections very close to the unit under test (UUT) as lead wires connecting the instruments can distort the signal. The solution we describe here involves the use of a field programmable gate array (FPGA) to implement the test instrument called a synthetic instrument (SI). SIs can be designed using VHDL or Verilog descriptions and "synthesized" into an FPGA. A variety of general-purpose instruments, such as signal generators, voltmeters, waveform analyzers can thus be synthesized, but the FPGA approach need not be limited to instruments with traditional instrument equivalents. Rather, more complex and peculiar test functions that pertain to high-speed I/O applications, such as bit error rate tests, SerDes tests, even USB 3.0 (running at 5 Gbps) protocol tests can be programmed and synthesized within an FPGA. By using specific-purpose test mechanisms for high-speed I/O the test engineer can reduce test development time. The synthetic instruments as well as the tests themselves can find applications in several UUTs. In some cases, the same test can be reused without any alteration. For example, a USB 3.0 bus is ubiquitous, and a test aimed at fault detection and diagnoses can be used as part of the test of any UUT that uses this bus. Additionally, parts of the test set may be reused for testing another high-speed I/O. It is reasonable to utilize some of the test routines used in a USB 3.0 test, in the development of a USB 3.1 (running at 10 Gbps), even if the latter has substantial differences in protocol. Many of the SI developed for one protocol can be reused as is, while other SIs may need to undergo modifications before reuse. The modifications will likely take less time and effort than starting from scratch. This paper illustrates an example of high-speed I/O testing, generalizes failure modes that are likely to occur in high-speed I/O, and offers a strategy for testing them with SIs within FPGAs. This strategy offers several advantages besides reusability, including tester proximity to the UUT, test modularization, standardization approaching an ATE-agnostic test development process, overcoming physical limitations of general-purpose test instruments, and utilization of specific-purpose test instruments. Additionally, test instrument obsolescence can be overcome by upgrading to ever-faster and larger FPGAs without losing any previously developed design effort. With SIs and tests scalable and upward compatible, the test engineer need not start test development for high-speed I/O from scratch, which will substantially reduce time and effort.
Used SMT Equipment | In-Circuit Testers
Agilent 83620B-001-002 Agilent/HP 83620B Synthesized Swept-Signal Generator, 0.01 - 20 GHz The Agilent 83620B synthesized sweeper for applications requiring the high performance and accuracy of a synthesized source and the speed and versatility
Used SMT Equipment | In-Circuit Testers
Agilent 83620B-001-002 Agilent/HP 83620B Synthesized Swept-Signal Generator, 0.01 - 20 GHz The Agilent 83620B synthesized sweeper for applications requiring the high performance and accuracy of a synthesized source and the speed and versatility
Used SMT Equipment | In-Circuit Testers
Agilent 83620B-001-002 Agilent/HP 83620B Synthesized Swept-Signal Generator, 0.01 - 20 GHz The Agilent 83620B synthesized sweeper for applications requiring the high performance and accuracy of a synthesized source and the speed and versatility
Used SMT Equipment | In-Circuit Testers
Agilent 8904A-001-002 Multifunction Synthesizer The 8904A Multifunction Synthesizer uses the latest VSLIC technology to create complex signals from six fundamental waveforms. The unit digitally synthesizes precise sine, square, triangle, ramp, w
New Equipment | Test Equipment
The HP Agilent 8720D Network Analyzer features a frequency range of 50 MHz to 20 GHz, a drastically faster processor compared to earlier versions, a built-in fast sweeping synthesized source, an integrated solid-state switching S-Parameter Test Set,
Technical Library | 2016-11-03 17:53:56.0
We present a novel method for fabricating a high-density carbon nanotube microelectrode array (MEA) chip. Vertically aligned carbon nanotubes (VACNTs) were synthesized by microwave plasma-enhanced chemical vapor deposition and thermal chemical vapor deposition. The device was characterized using electrochemical experiments such as cyclic voltammetry, impedance spectroscopy and potential transient measurements. Through-silicon vias (TSVs) were fabricated and partially filled with polycrystalline silicon to allow electrical connection from the high-density electrodes to a stimulator microchip.In response to the demand for higher resolution implants, we have developed a unique process to obtain a high-density electrode array by making the microelectrodes smaller in size and designing new ways of routing the electrodes to current sources.
