Electronics Forum | Wed Mar 15 12:05:24 EDT 2017 | emeto
Rob, Absolutely agree. Customer precedes standard. As you mentioned design engineers, I think that PCB design has the biggest influence on the voiding. Everything else we do is trying to fix bad PCB design.
Electronics Forum | Wed May 31 07:55:55 EDT 2017 | buckcho
In IPC it is said that the void % should be established between you and the customer. There is no number. There is only requirement for balls on BGA. I have a customer that agreed to 40% on D-packs which is okay for both us and them.
Electronics Forum | Sat Apr 28 08:04:29 EDT 2018 | shuhaib
Hi, please go through IPC 7093, its only for design and assembly process implementation for bottom termination components. its says up to 50% voids will not reduce ant electrical and thermal performance.
Electronics Forum | Tue Mar 14 12:22:20 EDT 2017 | pzappella
Hello, I was at a IMAPS conference last year 2016 and several presentations for QFN packages showed x ray images with high void levels of 30 to 50% with the best around 15% with solder paste. During the discussion it was mentioned that the auto in
Electronics Forum | Wed Mar 15 04:36:16 EDT 2017 | Rob
@ Sr.Tech, Any voiding means that the part of the package under the void is not forming a solid thermal interface with the PCB, therefore it's heatsinking capability is reduced. With the drive for smaller packages with higher power handling capabil
Electronics Forum | Wed Mar 15 09:53:58 EDT 2017 | rob
Hi Etimov, Understood that to us assembling parts that IPC is king, however it isn't neccesarily the bible for design engineers. We've had customers demand almost zero voiding, or had to use conductive epoxy to avoid it. For some of us solder joi
Electronics Forum | Wed Mar 15 10:21:08 EDT 2017 | pzappella
Hello Rob, I totally agree with you. Is this a real problem that is being shoved under the rug or just whatever voiding we get from a belt furnace is good enough. I think vacuum reflow can do much better but is a batch approach and not contin
Electronics Forum | Thu Mar 16 19:12:22 EDT 2017 | pzappella
Hi Rob, Thanks for the LED paper. I like the void area equations but I am puzzled, the paper did not say if the solder was a solder paste that would generate a lot of voids, or a fluxless preform or sinter material. The measured voiding level
Electronics Forum | Tue May 01 20:40:38 EDT 2018 | sarason
In the past I have worked on 600 Amp FET Blocks. The rule was no voids. The circuit board would be heavy copper. 4 times normal plating time. Not particularly high resolution on the board say 20 mils. To help with the heavy plating. The boards were t
Electronics Forum | Fri Mar 17 21:38:55 EDT 2017 | jlawson
I think the main driver is MTBF data driven by the Car OEMS, mainly german makers pushing this onto suppliers in supply chain. Vacuum soldering and void reduction is a hot topic for the leading electronics suppliers in Germany at the moment. Is not r
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