Electronics Forum | Mon Jun 24 22:39:25 EDT 2019 | sssamw
yes, the void should not expose the conductor or bridge the conductor, the coating there should be thick as IPC required but you need minimize the voids and bubbles. ALso for those small chips, a void or bubble on it means possible ECM, normlly shou
Electronics Forum | Wed Oct 14 01:17:40 EDT 2020 | SMTA-64386317
Data sheet allows of 250 DegC peak temperature and we are using below 240 DegC but still seeing high fal out. Manufacturer diagnose as BE charges loss due to heat. Hence, looking for anything extra could be done to minimize this defect. There is no w
Electronics Forum | Thu Dec 17 18:24:37 EST 2020 | SMTA-64387520
We use both in our selective soldering machine. Training is the most important concern. As long as you have well trained operators the risk is minimized.
Electronics Forum | Thu Aug 17 12:48:40 EDT 2023 | denism
Measure the temperature of the central and edge balls. There should be minimal difference in peak temperature and TAL offset. If not, correct reflow profile. For correct reflow profile your BGA mus be backed befor use.
Electronics Forum | Tue Oct 31 19:37:34 EDT 2023 | ttheis
That is true; it is not a fast process but it is selective and uses minimal material. Also true that the application consistency has to be checked and sometimes minor adjustments made at the beginning of a run. We have a program that checks for a con
Electronics Forum | Wed Feb 28 15:11:45 EST 2024 | emeto
Hello all, I have a flux over components that affects AOI results in reading the symbols on top of it. What would you recommend to minimize this effect?
Electronics Forum | Thu Jul 29 23:21:51 EDT 1999 | CH Lee
I received a request from customer to assemble ceramic substrate (alumina oxide)that printed with a low temperature Copper thick film conductor (the overglaze layer is polymer). The Copper pads are exposed without any coating. This ceramic substrate
Electronics Forum | Thu Jun 11 23:35:40 EDT 1998 | Scott McKee
| Does anybody know if a contraption exists that will minimize a PCB's tendency to become slightly bent after reflow? We have a new product that we're planning to assemble in a couple of months. The board is 9.7" by 13.4" and it is imperitive that
Electronics Forum | Sun Mar 29 22:55:06 EST 1998 | Yoshi Kuni
| I would like to hear from anyone producing high mix (~200 modules) with low volumes (5-2000 per year) using an automatic line running lot sizes in the 5-50 range. We are engaged in an investigation to invest in this capability. A view into the or
Electronics Forum | Fri Feb 14 08:08:45 EST 2003 | Louis
First of all I would like to say that my English is so-so but I will try to help you. FOLLOW THOSE STEPS AND YOU WILL BE OK. 1-- select learn fiducial option then enter minimal value to fiducial width and height (enter 0 and you will g
