The PCB Footprint Expert is a powerful CAD library development tool powered by our own proprietary CAD LEAP Technology (Libraries Enhanced with Automated Preferences). It is packed with very powerful advanced library management features that cuts foo
SIPAD Solid Solder Deposit (ssd) is a Siemens patented process that pre loads the pc board surface mount pads with solder in a solid form. Boards are printed, reflowed without components producing a predictable repeatable meniscus. SIPAD boards a
Electronics Forum | Wed Jul 23 03:04:57 EDT 2008 | gfro
Hello, We are using a PCB with thickness 3.2mm 4 layer and lot of through hole via's of diameter 0.4mm. We specified our PCB vendor to do plugging. Now we have big problems, that after 1..4 weeks we measure a low resistance between track's/via's of
Electronics Forum | Thu Jan 06 06:15:49 EST 2005 | mattkehoe
We need some opinions about a situation that is causing problems in our process. The pcb's in question are .125 thick with a HASL finish. The boards are coming in with a large amount of solder trapped inside the via holes. Sometimes this solder is ac
Industry News | 2012-09-10 12:48:23.0
To help companies gain the most out of HDI technology, Raytheon is sponsoring the “IPC HDI Conference: Advancements in Materials, Processes and Applications,” October 24–25 in Los Angeles, Calif.
Industry News | 2001-11-27 13:09:48.0
IPC has announced its tutorial and workshop schedule for IPC Printed Circuits Expo 2002. A total of 34 courses are scheduled, including 15 full-day tutorials on March 24-25, and 19 half-day workshops, which will take place on March 25 and 28.
Technical Library | 2019-10-10 00:26:28.0
Voids are a plague to our electronics and must be eliminated! Over the last few years we have studied voiding in solder joints and published three technical papers on methods to "Fill the Void." This paper is part four of this series. The focus of this work is to mitigate voids for via in pad circuit board designs. Via holes in Quad Flat No-Lead (QFN) thermal pads create voiding issues. Gasses can come out of via holes and rise into the solder joint creating voids. Solder can also flow down into the via holes creating gaps in the solder joint. One method of preventing this is via plugging. Via holes can be plugged, capped, or left open. These via plugging options were compared and contrasted to each other with respect to voiding. Another method of minimizing voiding is through solder paste stencil design. Solder paste can be printed around the via holes with gas escape routes. This prevents gasses from via holes from being trapped in the solder joint. Several stencil designs were tested and voiding performance compared and contrasted. In many cases voiding will be reduced only if a combination of mitigation strategies are used. Recommendations for combinations of via hole plugging and stencil design are given. The aim of this paper is to help the reader to "Fill the Void."
Technical Library | 2016-11-30 15:53:15.0
The use of microvias in Printed Circuit Boards (PCBs) for military hardware is increasing as technology drives us toward smaller pitches and denser circuitry. Along with the changes in technology, the industry has changed and captive manufacturing lines are few and far between. As PCBs get more complicated, the testing we perform to verify the material was manufactured to our requirements before they are used in an assembly needs to be reviewed to ensure that it is sufficient for the technology and meets industry needs to better screen for long-term reliability. The Interconnect Stress Testing (IST) protocol currently used to identify manufacturing issues in plated through holes, blind, or buried vias are not necessarily sufficient to identify problems with microvias. There is a need to review the current IST protocol to determine if it is adequate for finding bad microvias or if there is a more reliable test that will screen out manufacturing inconsistencies. The objective of this research is to analyze a large population of PCB IST coupons to determine if there is a more effective IST test to find less reliable microvias in electrically passing PCB product and to screen for manufacturing deficiencies. The proposed IST test procedure will be supported with visual inspection of corresponding microvia cross sections and Printed Wiring Assembly (PWA) acceptance test results. The proposed screening will be shown to only slightly affect PCB yield while showing a large benefit to screening before PCBs are used in an assembly.
The PCB Footprint Expert is a powerful CAD library development tool powered by our own proprietary CAD LEAP Technology (Libraries Enhanced with Automated Preferences). It is packed with very powerful advanced library management features that cuts foo
DescriptionThe Electrovert® Electra™ is an advanced, meticulously engineered wave soldering system designed for high-mass and high-volume manufacturers. Although intended for maximum throughput requirements, the Electra also offers maximum process fl
Training Courses | ON DEMAND | | IPC-600 Trainer (CIT)
The Certified IPC-600 Trainer (CIT) courses recognize individuals as qualified trainers in the area of quality assurance of bare printed circuit boards and prepare them to deliver Certified IPC-600 (CIS) training.
SMT Express, Volume 2, Issue No. 3 - from SMTnet.com Volume 2, Issue No. 3 Thursday, March 16, 2000 Featured Article Return to Front Page Stencil Design for Mixed Technology Through-hole / SMT Placement and Reflow by William E. Coleman, Photo
ASYMTEK Products | Nordson Electronics Solutions | https://www.nordson.com/en/divisions/polymer-processing-systems/information/barrel-cost-of-ownership
quality, and allow for very large barrels as well as standard sizes. Short of employing special metallurgical techniques, it is a challenge for most processors to prove out a barrel inlay
Surface Mount Technology Association (SMTA) | https://www.smta.org/knowledge/journal.cfm
. SMTA JOURNAL ARTICLES: 1999 - Present Allow time for larger file downloads. YEAR VOL. TITLE AUTHOR 2019 32-3 Characterization of Soldered Plated Through Holes (PTHs
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