Technical Library | 2023-01-17 18:04:51.0
As a manufacturing technology, SMT has acquired a "heritage" of widely accepted assumptions about its processes. However, yesterday'spractices are continually confronted by the shifting paradigms of today's production line.
Technical Library | 2023-01-17 17:12:33.0
Reflowed indium metal has for decades been the standard for solder thermal interface materials (solder TIMs or sTIMs) in most high-performance computing (HPC) TIM1 applications. The IEEE Heterogeneous Integration Thermal roadmap states that new thermal interface materials solutions must provide a path to the successful application of increased total-package die areas up to 100cm2. While GPU architectures are relatively isothermal during usage, CPU hotspots in complex heterogeneously-integrated modules will need to be able to handle heat flux hotspots up to 1000W/cm2 within the next two years. Indium and its alloys are used as reflowed solder thermal interface materials in both CPU and GPU "die to lid/heat spreader" (TIM1) applications. Their high bulk thermal conductivity and proven long-term reliability suit them well for extreme thermomechanical stresses. Voiding is the most important failure mode and has been studied by x-ray. The effects of surface pretreatment, pressure during reflow, solder flux type/fluxless processing, and preform design parameters, such as alloy type, are also examined. The paper includes data on both vacuum and pressure (autoclave) reflow of sTIMs, which is becoming necessary to meet upcoming requirements for ultralow voiding in some instances.
Technical Library | 2023-01-17 17:58:36.0
Heterogeneous integration has become an important performance enabler as high-performance computing (HPC) demands continue to rise. The focus to enable heterogeneous integration scaling is to push interconnect density limit with increased bandwidth and improved power efficiency. Many different advanced packaging architectures have been deployed to increase I/O wire / area density for higher data bandwidth requirements, and to enable more effective die disaggregation. Embedded Multi-die Interconnect Bridge (EMIB) technology is an advanced, cost-effective approach to in-package high density interconnect of heterogeneous chips, providing high density I/O, and controlled electrical interconnect paths between multiple dice in a package. In emerging architectures, it is required to scale down the EMIB die bump pitch in order to further increase the die-to-die (D2D) communication bandwidth. Aa a result, bump pitch scaling poses significant challenges in the plated solder bump reflow process, e.g., bump height / coplanarity control, solder wicking control, and bump void control. It's crucial to ensure a high-quality solder bump reflow process to meet the final product reliability requirements. In this paper, a combined formic acid based fluxless and vacuum assisted reflow process is developed for fine pitch plated solder bumping application. A high-volume production (HVM) ready tool has been developed for this process.
Technical Library | 2023-01-17 17:27:13.0
Reflow profile has significant impact on solder joint performance because it influences wetting and microstructure of the solder joint. The degree of wetting, the microstructure (in particular the intermetallic layer), and the inherent strength of the solder all factor into the reliability of the solder joint. This paper presents experimental results on the effect of reflow profile on both 63%Sn 37%Pb (SnPb) and 96.5%Sn 3.0%Ag 0.5%Cu (SAC 305) solder joint shear force. Specifically, the effect of the reflow peak temperature and time above solder liquidus temperature are studied. Nine reflow profiles for SAC 305 and nine reflow profiles for SnPb have been developed with three levels of peak temperature (230 o C, 240 o C, and 250 o C for SAC 305; and 195 o C, 205 o C, and 215 o C for SnPb) and three levels of time above solder liquidus temperature (30 sec., 60 sec., and 90 sec.). The shear force data of four different sizes of chip resistors (1206, 0805, 0603, and 0402) are compared across the different profiles. The shear force of the resistors is measured at time 0 (right after assembly). The fracture surfaces have been studied using a scanning electron microscopy (SEM) with energy dispersive spectroscopy (EDS)
Technical Library | 2019-08-19 09:46:13.0
Boundary scan is a method for testing interconnects on printed circuit boards (PCBs) or sub-blocks inside an integrated circuit. It has rapidly become the technology of choice for building reliable high technology electronic products with a high degree of testability. Due to the low-cost and integrated circuit (IC) level access capabilities of boundary scan, its use has expanded beyond traditional board test applications into product design and service.
Technical Library | 2020-04-14 15:49:38.0
The number of through-hole components on printed circuit boards (PCB) has declined significantly over the last decade. Miniaturization in electronics has resulted in less THT (through-hole technology) and leads with a finer pitch. For this reason, the soldering of these components has also changed from wave soldering to Point-to-point selective soldering. Soldering these small, fine-pitch components is a challenge when surface mount components (SMD) are positioned very close to THT components on the PCB layout. This study, done in cooperation with a large automotive EMS customer, defines the process windows for through-hole technology for fine-pitch components. It determines what is feasible to solder and defines layout design parameter that make soldering possible with SMD areas and other components on the assembly.
Technical Library | 2019-05-23 10:27:13.0
The technical tips have offered valuable details and techniques into various aspects of electronics manufacturing. This has been validated by the reader responses concurring with our assessments, offering additional insight, or in some rare cases, stating divergent points of view on any particular matter. In a bit of a strategic departure from the normal range of electronic manufacturing topics, ACI Technologies,Inc. would like our readers to consider the importance of being well prepared in the arena of designed experiments in order to properly qualify a manufacturing process. This particular topic has relevance because of the associated scope of work ACI Technologies encounters in numerous projects from material R&D to manufacturing process optimization, which require appropriate experimental designs to ascertain the significant data.
Technical Library | 2020-05-08 18:22:31.0
A customer contacted the Helpline to perform analysis on a lead-free assembly which exhibited intermittent functionality. The lead-free assembly exhibiting intermittent functionality when pressure was applied to the ball grid array (BGA) packages. Industrial adaptation of a Restriction of Hazardous Substances (RoHS) compliant solder standard has created a new host of failure modes observed in lead-free assemblies. Pad cratering occurs when fractures propagate along the epoxy resin layer on the underside of the BGA connecting pads. While originating from process, design, and end use conditions, it is the combination of a rigid lead-free solder with inflexible printed circuit board (PCB) laminates that has advanced the prevalence of this condition. Pad cratering is simply the result of mechanical stress exceeding material limitations.
Technical Library | 2019-07-01 10:44:11.0
In the electronics industry of today, companies emphasize better quality, lower cost, and shorter lead time on their products in order to keep up with their competitors. ACI Technologies (ACI) has been utilizing Computer Aided Design (CAD), Computer Aided Manufacturing(CAM), and Computer Aided Engineering (CAE) in its development of advanced electronics systems. CAD utilizes computer systems to assist in the creation, modification, analysis, and optimization of a design [1].
Technical Library | 2019-05-30 11:04:03.0
There exists a need to efficiently remove heat from power electronics within power systems to enhance performance. Thermal management is a critical function to that operation. Reducing the junction temperature of semiconductor power electronic devices enables them to operate at higher currents. Lowering operating temperatures reduces the thermal stress on electronic devices, which improves efficiency and reduces failures. To improve the heat removal process, the current heat transfer design of a power system has been analyzed and a variety of thermal interface materials (TIMs) and cold plate technologies have been evaluated. This paper will review some of these results.
