Electronics Forum: solder and joint (Page 146 of 388)

Criteria for Min Thickness regarding Large and Small pads

Electronics Forum | Mon Jun 30 08:55:31 EDT 2008 | davef

It will be tough to find a dimensional thickness specification for HASL. IPC-6012 Table 3-2, line "Fused tin-lead or solder coat - Coverage and Solderable" states the requirement that there has to be complete coverage of solder on the land, and it mu

No clean and 100 Mbps Fast Ethernet Transceiver

Electronics Forum | Tue Sep 30 13:55:37 EDT 2008 | realchunks

How do you normally solder it?

wave soldering surface mount tantalum and ceramic capacitors

Electronics Forum | Thu Feb 04 09:09:07 EST 1999 | dave

Can anyone help me with the pros and cons of trying to wave solder tantalum and large (1812) ceramic capacitors. I do know that one may see fractures on larger cermaic caps, but have not seen much on the tantalums. Any insight as to what problems I c

environment Operational deg-C and RH% for Paste Printer

Electronics Forum | Thu Jun 06 15:52:38 EDT 2002 | dason_c

It is normal recommended by the paste supplier. Indium paste claim that it can worked on high temp/RH area. Also, check Aim solder web site and they have a good solder paste handling guideline. Internally, we control our environment not exceed 27C

Lead Free Solder Reliability Issues in Military and Aerospace

Electronics Forum | Wed Jan 26 12:36:14 EST 2005 | Rob Wilson

I saw in a presentation that military testing of lead-free soldering for reliability has not gone well. Basically, unlike commercial applications where the alloys performed better they did worse when under the more extreme military and aerospace con

PB and PB Free on same screen printer

Electronics Forum | Fri Oct 12 08:19:12 EDT 2007 | davef

Michael We know you're just trying to have fun by getting us to respond. Going along with the game, if your solder is more expensive, requires more energy to melt, produces less reliable solder connectiuons, and is worse for the environment; how to

Tinned leads and where the component body is defined

Electronics Forum | Thu Sep 03 22:03:32 EDT 2020 | SMTA-64386139

Both conditions are acceptable for this bottom brazed flat pack package. The solder coverage must be within 0.070 inch of the lead/package interface per MIL-PRF-38535, paragraph A3.5.6.3.4.a. While that requirement could allow for a gold gap near t

Re: Wave Soldering 14 and 16 Pin SOICs

Electronics Forum | Wed Mar 10 13:53:13 EST 1999 | Vincent Vega

| We will wave solder a board with SOIC14 and SOIC16 parts on the bottom. It has been difficult to find any specific wave solder process recommendations from manufacturers of the SOICs. The pad geometry utilizes theiving pads on both sides to reduce

Line release of post reflow AOI and AXI

Electronics Forum | Mon Sep 22 17:02:58 EDT 2008 | hegemon

You are on the right track Ismir. Essentially however, as the programmer of the machine, I am the one that creates the PCB with the errors to benchmark the settings for the machine. No secret lab though! :-) Easy enough for most any AOI machine to

Re: wave soldering surface mount tantalum and ceramic capacitors

Electronics Forum | Fri Feb 05 09:39:58 EST 1999 | Dave F

| Can anyone help me with the pros and cons of trying to wave | solder tantalum and large (1812) ceramic capacitors. I do | know that one may see fractures on larger cermaic caps, but have not seen much on the tantalums. Any insight as to what proble


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