Electronics Forum | Mon Oct 25 15:45:11 EDT 1999 | Dave F
Joe: Lemme see, you�re talking about controlling your manufacturing process within 4.6 defects per 100 opportunities or a 4,600 dpmo rate, a cumulative 99.95 acceptance rate, or a �2 sigma process, right? So, it�s fairly basic stuff, eh? First, yo
Electronics Forum | Tue Jul 27 16:44:31 EDT 1999 | Earl Moon
| | | Presently protos of micro-bgas (80i/o) pitch .030/.031 | | | 12BGA per assembly | | | | | | The board is a (.062, 4 layers) FR-4 using Dry film | | | Pads .014inch | | | Vias within footprint .020inch | | | Vias to be filled by bottom side(sol
Electronics Forum | Tue Jul 27 17:23:45 EDT 1999 | M.L
| | | | Presently protos of micro-bgas (80i/o) pitch .030/.031 | | | | 12BGA per assembly | | | | | | | | The board is a (.062, 4 layers) FR-4 using Dry film | | | | Pads .014inch | | | | Vias within footprint .020inch | | | | Vias to be filled by b
Electronics Forum | Wed Jun 03 21:25:33 EDT 1998 | John Allan
| Hello: | BACKGROUD: SMT components soldered on the top-side of boards that also require wave soldering have the potential to reflow during wave soldering. Reflowing these components during wave soldering is not good. It can cause cold joints, op
Electronics Forum | Thu Jun 04 08:32:21 EDT 1998 | Dave F
| | Hello: | | BACKGROUD: SMT components soldered on the top-side of boards that also require wave soldering have the potential to reflow during wave soldering. Reflowing these components during wave soldering is not good. It can cause cold joints
Electronics Forum | Mon Sep 20 13:04:25 EDT 2004 | davef
The Intel BGA Developer�s Guide [ http://developer.intel.com/design/packtech/ch_14.pdf ] says: 14.8.3.3 Plated Through Hole (PTH) Isolation Regardless of the technique used for the mounting pads shape or definition, isolation of the plated through h
Electronics Forum | Thu Apr 15 10:05:50 EDT 2010 | dwonch
Hi all, Long story ahead.... We are having issues with board vendors on some of our higher layer count (thick) boards. Specifically under BGAs with high aspect ratio vias (14:1). We are using ENIG finish and a lead free process. Basically we get t
Electronics Forum | Tue Jun 05 03:56:52 EDT 2001 | JohnW
Flip Chip/uBGA Underfill Visual Standards The aim of this document is to produce some draft text and then select photographs to make up a draft visual standard for inspection. There is also a need to produce some reference material for C Scan image
Electronics Forum | Fri Sep 10 11:45:09 EDT 1999 | Scott S. Snider
| scott. | I appreciate your sincere answer. | would tell me the hint about printer if i's possible | To tune our smt process we have to know what is the major X's | for defect. To know major X's with DOE we need a good measurement equipment.
Electronics Forum | Tue Jul 27 17:54:37 EDT 1999 | Earl Moon
| | | | | Presently protos of micro-bgas (80i/o) pitch .030/.031 | | | | | 12BGA per assembly | | | | | | | | | | The board is a (.062, 4 layers) FR-4 using Dry film | | | | | Pads .014inch | | | | | Vias within footprint .020inch | | | | | Vias to
