Technical Articles From Flex (Flextronics International)

THE IMPACT OF VIA AND PAD DESIGN ON QFN ASSEMBLY

Jul 24, 2024 | Jennifer Nguyen, David Geiger and Anwar Mohammed

Quad Flat No-Lead (QFN) packages has become very popular in the industry and are widely used in many products. These packages have different size and pin counts, but they have a common feature: thermal pad at the bottom of device. The thermal pad of the leadless QFN provides efficient heat dissipation from the component to PCB. In many cases, arrays of the thermal via under the component is used to dissipate heat from the device. However, thermal vias can create more voids or result in solder protrusion onto the secondary side....

AOI Capabilities Study with 03015 Component

Jan 23, 2019 | David Geiger, Vincent Nguyen, Hung Le, Stephen Chen, Robert Pennings, Christian Biederman, Zhen (Jane) Feng, Ph. D., Alan Chau, Weifeng Liu, Ph. D., William Uy, Anwar Mohammed, Mike Doiron

Automated Optical Inspection (AOI) is advantageous in that it enables defects to be detected early in the manufacturing process, reducing the Cost of Repair as the AOI systems identify the specific components that are failing removing the need for any additional test troubleshooting1-3. Because of this, more Electronic Contract Manufacturing Services (EMS) companies are implementing AOI into their SMT lines to minimize repair costs and maintain good process and product quality, especially for new component types. This project focuses on the testing of component package 03015 which is challenging for AOI....

Nondestructive Inspection of Underfill Layers Stacked up in Ceramics-Organics-Ceramics Packages with Scanning Acoustic Tomography (SAT)

Jun 15, 2017 | Justin Zeng, Francoise Sarrazin, Jie Lian, Ph.D., Zhen (Jane) Feng, Ph.D., Lea Su, Dennis Willie, David Geiger - Flex International Inc., Masafumi Takada, Natsuki Sugaya - Hitachi Power Solutions, George Tint, Ph.D. - HDI Solutions

Ceramics packages are being used in the electronics industry to operate the devices in harsh environments. In this paper we report a study on acoustic imaging technology for nondestructively inspecting underfill layers connecting organic interposers sandwiched between two ceramics substrates.

First, we inspected the samples with transmission mode of scanning acoustic tomography (SAT) system, an inspection routine usually employed in assembly lines because of its simpler interpretation criteria: flawed region blocks the acoustic wave and appears darker. In this multilayer sample, this approach does not offer the crucial information at which layer of underfill has flaws. To resolve this issue, we use C-Mode Scanning in reflection mode to image layer by layer utilizing ultrasound frequencies from 15MHz to 120MHz. Although the sample is thick and contains at least 5 internal material interfaces, we are able to identify defective underfill layer interfaces....

Press Fit Technology Roadmap and Control Parameters for a High Performance Process

Oct 27, 2016 | Jose Becerra, Dennis Willie and Murad Kurwa

Press-fit technology is a proven and widely used and accepted interconnection method for joining electronics assemblies. Printed Circuit Board Assembly Systems and typical functional subassemblies are connected through press-fit connectors.

The Press-Fit Compliant Pin is a proven interconnect termination to reliably provide electrical and mechanical connections from a Printed Circuit Board to an Electrical Connector. Electrical Connectors are then interconnected together providing board to board electrical and mechanical inter-connection. Press-Fit Compliant Pins are housed within Connectors and used on Backplanes, Mid-planes and Daughter Card Printed Circuit Board Assemblies. High reliability OEM (Original Equipment Manufacturer) computer designs continue to use press-fit connections to overcome challenges associated with soldering, rework, thermal cycles, installation and repair.

This paper investigates the technical roadmap for press fit technology, putting special attention to main characteristics such, placement and insertion, inspection, repair, pin design trends, challenges and solutions. Critical process control parameters within an assembly manufacturing are highlighted....

Reliability Study of Low Silver Alloy Solder Pastes

Sep 01, 2016 | Jennifer Nguyen, David Geiger and Murad Kurwa

Sn3.0Ag0.5Cu (SAC305) is currently the most popular near eutectic lead-free alloy used in the manufacturing processes. Over the last several years, the price of silver has dramatically increased driving a desire for lower silver alloy alternatives. As a result, there is a significant increase in the number of alternative low/no silver lead-free solder alloys available in the industry recently. Our previous study showed that many alternative low silver solder paste materials had good printing and wetting performance as compared to SAC305 solder pastes. However, there is lack of information on the reliability of alternative alloy solder joints assembled using alternative low silver alloy solder pastes.

In this paper, we will present the reliability study of lead-free solder joints reflowed using various lead-free alloy solder pastes after thermal cycling test (3000 cycles, 0°C to 100°C). Six different lead-free pastes were investigated. SAC305 solder joints were used as the control. Low and no silver solder pastes and a low temperature SnBiAg solder pastes were also included....

Selective Reflow Rework Process

Aug 18, 2016 | Omar García, Enrique Avelar, C. Sanchez, M. Carrillo, O. Mendoza, J. Medina, Zhen (Jane) Feng,Ph.D., Murad Kurwa

The Selective Reflow Rework Process is an approach to improving the high volume rework process, increasing process capabilities and process repeatability by using a standard reflow oven of 12 zones, pick and place machinery, semi-automated printing gear and Solder Paste Inspection (SPI) implementations. This approach was able to reduce the amount of rework equipment by more than half. Our human resource requirements (indirect and direct labor) were cut by more than 50% and our rolled throughput yield increased from 68.9% to 84.14%. The Selective Reflow Rework Process is less reliant upon operators and has become a repeatable, stable rework process....

A Case Study on Evaluating Manual and Automated Heat Sink Assembly Using FEA and Testing

Jun 23, 2016 | Michael Sumalinog, Jesus Tan, Murad Kurwa; AEG, Flex.

Proper assembly of components is critical in the manufacturing industry as it affects functionality and reliability. In a heat sink assembly, a detailed manual process is often utilized. However, an automated fixture is used whenever applicable.

This paper will illustrate the use of strain gauge testing and Finite Element Analysis (FEA) as a simulation tool to evaluate and optimize the heat sink assembly process by manual and automated methods. Several PCBAs in the production line were subjected to the manual and automated assembly process. Strain gauge testing was performed and FEA models were built and run. Results were compared with the goal of improving the FEA model. The updated FEA model will be used in simulating different conditions in assembly. Proposed improvement solutions to some issues can also be verified through FEA....

Characterization of Solder Defects on Package on Packages with AXI Systems for Inspection Quality Improvement

May 30, 2016 | Zhen Feng, Ph. D., David Geiger, Weifeng Liu, Ph. D., Anwar Mohammed, Murad Kurwa, AEG, Flextronics, George Tint Ph. D., Saki America.

As a part of series of studies on X-Ray inspection technology to quantify solder defects in BGA balls, we have conducted inspection of 3 level POP package by using a new AXI that capable of 3D-CT imaging. The new results are compared with the results of earlier AXI measurements. It is found that 3D measurements offer better defect inspection quality, lower false call and escapes....

3D Assembly Process a Look at Today and Tomorrow

Apr 21, 2016 | David Geiger, Georgie Thein; AEG, Flextronics International Inc.

The world of electronics continues to increase functional densities on products. One of the ways to increase density of a product is to utilize more of the 3 dimensional spaces available. Traditional printed circuit boards utilize the x/y plane and many miniaturization techniques apply to the x/y space savings, such as smaller components, finer pitches, and closer component to component distances.

This paper will explore the evolution of 3D assembly techniques, starting from flexible circuit technology, cavity assembly, embedded technology, 3 dimensional surface mount assembly, etc....

Study on Solder Joint Reliability of Fine Pitch CSP

Dec 31, 2015 | Yong Hill Liang, Hank Mao, YongGang Yan, Jindong (King) Lee; AEG, Flextronics International.

Today's consumer electronic product are characterized by miniatuization, portability and light weight with high performance, especially for 3G mobile products. In the future more fine pitch CSPs (0.4mm) component will be required. However, the product reliability has been a big challenge with the fine pitch CSP. Firstly, the fine pitch CSPs are with smaller solder balls of 0.25mm diameter or even smaller. The small solder ball and pad size do weaken the solder connection and the adhesion of the pad and substrate, thus the pad will peel off easily from the PCB substrate. In addition, miniature solder joint reduce the strength during mechanical vibration, thermal shock, fatigue failure, etc. Secondly, applying sufficient solder paste evenly on the small pad of the CSP is difficult because stencil opening is only 0.25mm or less. This issue can be solved using the high end type of stencil such as Electroforming which will increase the cost....

Study of Various PCBA Surface Finishes

Nov 25, 2015 | Georgie Thein, David Geiger, and Murad Kurwa.

In this study various printed circuit board surface finishes were evaluated, including: organic solderability preservative (OSP), plasma finish (PF), immersion silver (IAg), electroless nickel / immersion silver (ENIS), electroless nickel / immersion gold hi-phosphorus (ENIG Hi-P), and electroless nickel / electroless palladium / immersion gold (ENEPIG). To verify the performance of PF as a post-treatment option, it was added to IAg, ENIG Hi-P, and ENEPIG to compare with non-treated. A total of nine groups of PCB were evaluated. Each group contains 30 boards, with the exception on ENIS where only 8 boards were available....

Gold Stud Bump Flip Chip Bonding on Molded Interconnect Devices

Sep 23, 2015 | Dick Pang, Weifeng Liu, Anwar Mohammed, Elissa Mckay, Teresita Villavert and Murad Kurwa

A molded interconnect device (MID) is an injection molded thermoplastic substrate which incorporates a conductive circuit pattern and integrates both mechanical and electrical functions. (...) Flip chip bonding of bare die on MID can be employed to fully utilize MID’s advantage in device miniaturization. Compared to the traditional soldering process, thermo-compression bonding with gold stud bumps provides a clear advantage in its fine pitch capability. However, challenges also exist. Few studies have been made on thermocompression bonding on MID substrate, accordingly little information is available on process optimization, material compatibility and bonding reliability. Unlike solder reflow, there is no solder involved and no “self-alignment,” therefore the thermo-compression bonding process is significantly more dependent on the capability of the machine for chip assembly alignment....

Reliability Study of Bottom Terminated Components

Jul 14, 2015 | Jennifer Nguyen, Hector Marin, David Geiger, Anwar Mohammed, and Murad Kurwa

Bottom terminated components (BTC) are leadless components where terminations are protectively plated on the underside of the package. They are all slightly different and have different names, such as QFN (quad flat no lead), DFN (dual flat no lead), LGA (land grid array) and MLF (micro lead-frame. BTC assembly has increased rapidly in recent years. This type of package is attractive due to its low cost and good performance like improved signal speeds and enhanced thermal performance.

However, bottom terminated components do not have any leads to absorb the stress and strain on the solder joints. It relies on the correct amount of solder deposited during the assembly process for having a good solder joint quality and reliable reliability. Voiding is typically seen on the BTC solder joint, especially on the thermal pad of the component. Voiding creates a major concern on BTC component’s solder joint reliability. There is no current industry standard on the voiding criteria for bottom terminated component. The impact of voiding on solder joint reliability and the impact of voiding on the heat transfer characteristics at BTC component are not well understood. This paper will present some data to address these concerns....

Miniaturization with Help of Reduced Component to Component Spacing

Mar 12, 2015 | Jonas Sjoberg, Ranilo Aranda, David Geiger, Anwar Mohammed, Murad Kurwa - Flextronics Advanced Engineering Group

Miniaturization and the integration of a growing number of functions in portable electronic devices require an extremely high packaging density for the active and passive components. There are many ways to increase the packaging density and a few examples would be to stack them with Package on Package (PoP), fine pitch CSP's, 01005 and last but not least reduced component to component spacing for active and passive components (...)

This paper will discuss different layouts, assembly and material selections to reduce component to component spacing down to 100-125um (4-5mil) from today’s mainstream of 150-200um (6-8mil) component to component spacing....

Numerical Study on New Pin Pull Test for Pad Cratering Of PCB

Feb 19, 2015 | Billy Hu, Jesus Tan

Pad cratering is an important failure mode besides crack of solder joint as it’ll pass the regular test but have impact on the long term reliability of the product. A new pin pull test method with solder ball attached and positioning the test board at an angle of 30º is employed to study the strength of pad cratering. This new method clearly reveals the failure mechanism. And a proper way to interpret the finite element analysis (FEA) result is discussed. Impact of pad dimension, width and angle of copper trace on the strength is included. Some findings not included in previous research could help to guide the design for better performance...

Head in Pillow X-ray Inspection at Flextronics

Dec 18, 2014 | Alejandro Castellanos, Adalberto Gutierrez, Gilberto Martin, Matthew Vandiver, Ranga Dematampitiya, Hung Le, Elliott Le, Phuong Chau, Hao Cui, An Qi Zhao, Wei Bing Qian, Fuqing Li, Jacky Yao, Jiyang Zhang, Leonard Brisan, Cristian Gurka, Shane Young

Manufacturing technology faces challenges with new packages/process when confronting the need for high yields. Identifying product defects associated with the manufacturing process is a critical part of electronics manufacturing. In this project, we focus on how to use AXI to identify BGA Head-in-Pillow (HIP), which is challenging for AXI testing. Our goal is to help us understand the capabilities of current AXI machines....

Assembly Process Feasibility of Low/No Silver Alloy Solder Paste Materials

Oct 02, 2014 | Jennifer Nguyen Ranilo Aranda, David Geiger, and Murad Kurwa

Sn3.0Ag0.5Cu (SAC305) is the most popular near eutectic lead-free alloy used in the manufacturing processes. Over the last several years, the price of silver has dramatically increased driving a desire for lower silver alloy alternatives. As the results, there is a significant increase in the number of alternative low/no silver lead-free solder alloys available in the industry recently.

In this paper, we'll present the performance and process capability of various low/no silver alloy solder pastes. Data from printability, wetting test, slump test, solder ball test, voiding, etc… will be discussed and compared with the control SAC305 solder paste. Benefits and concerns of using low/no silver alloy solder paste materials will also be addressed....

Using Automated 3D X-Ray Inspection to Detect BTC Defects

Jul 25, 2013 | Barbara Koczera, An Qi Zhao

Bottom-termination components (BTC), such as QFNs, are becoming more common in PCB assemblies. These components are characterized by hidden solder joints. How are defects on hidden DFN joints detected? Certainly, insufficient solder joints on BTCs cannot be detected by manual visual inspection. Nor can this type of defect be detected by automated optical inspection; the joint is hidden by the component body. Defects such as insufficients are often referred to as "marginal" defects because there is likely enough solder present to make contact between the termination on the bottom-side of the component and the board pad for the component to pass in-circuit and functional test. Should the board be subjected to shock or vibration, however, there is a good chance this solder connection will fracture, leading to an open connection....

Application Of Build-in Self Test In Functional Test Of DSL

May 23, 2012 | YaJun Gu, Ye Qin, ZhiJun Wang, David Wei, Andrew Ho, Stephen Chen, Zhen (Jane) Feng Ph. D., Murad Kurwa

first published in the 2012 IPC APEX EXPO technical conference proceedings. BIST (build-in self test ) is the technique of designing additional hardware and software features into integrated circuits to allow them to perform self-testing, i.e., testing of...

Effects of Reflow Profile and Thermal Conditioning on Intermetallic Compound Thickness for SnAgCu Soldered Joints

Apr 29, 2010 | Jianbiao Pan, Tzu-Chien Chou, Jasbir Bath, Dennis Willie, Brian J. Toleno

The purpose of this paper is to investigate the effects of reflow time, reflow peak temperature, thermal shock and thermal aging on the intermetallic compound (IMC) thickness for Sn3.0Ag0.5Cu (SAC305) soldered joints....

Drop Impact Reliability of Edge-bonded Lead-free Chipscale Packages

Mar 30, 2010 | Andrew Farris, Jianbiao Pan, Albert Liddicoat, Michael Krist, Nicholas Vickers, Brian J.Toleno, Dan Maslyk, Dongkai Shangguan, Jasbir Bath, Dennis Willie, David A. Geiger.

This paper presents the drop test reliability results for edge-bonded 0.5mm pitch lead-free chip scale packages (CSPs) on a standard JEDEC drop reliability test board....