Technical Articles From Omg Electrochemicals / Macdermid Alpha
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3 technical articles added by Omg Electrochemicals / Macdermid Alpha
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Improved QFN Reliability by Flank Tin Plating Process after Singulation
Aug 04, 2023 | John Ganjei
The process of singulating IC packages such as Quad Flat Pack No-Lead (QFNs) by either a sawing or punching operation results in exposed copper on the sidewalls. This exposed copper surface can oxidize leading to poor or no solder wetting up the sidewall during the assembly operation. The consequence of this oxidized copper surface is either incomplete or no solder fillet formation during the PCB mounting operation resulting in solder joint reliability concerns. Currently, JEDEC and IPC assembly standards do not specify a toe fillet for assembly. However, several component manufacturers have requested a toe fillet solderability process which would improve current QFN reliability by ensuring toe fillet solder coverage. A process whereby tin is plated on the copper sidewall of the QFN after singulation has been developed to improve toe fillet solderability. Several assembly studies have been conducted which demonstrate improved QFN reliability due to the use of this toe fillet solderability process. The plating process, toe fillet inspection and improved QFN reliability after assembly due to the use of this toe fillet solderability is described....
A Process For Improved QFN Reliability
Aug 04, 2023 | Lenora Toscano, John Ganjei, Ph.D, Richard Retallick, and Gu Hong, Ph.D
The process of singulating IC packages such as Quad Flat Pack No-Lead (QFNs) by either a sawing or punching operation results in exposed copper on the sidewalls. This exposed copper surface can oxidize leading to poor or no solder wetting up the sidewall during the assembly operation. The consequence of this oxidized copper surface is either incomplete or no solder fillet formation during the PCB mounting operation resulting in solder joint reliability concerns. Currently, JEDEC and IPC assembly standards do not specify a toe fillet for assembly. However, several component manufacturers have requested a toe fillet solderability process which would improve current QFN reliability by ensuring toe fillet solder coverage A process whereby tin is plated on the copper sidewall of the QFN after singulation has been developed to improve toe fillet solderability. Several assembly studies have been conducted which demonstrate improved QFN reliability due to the use of this toe fillet solderability process. The plating process, toe fillet inspection and improved QFN reliability after assembly due to the use of this toe fillet solderability is described....
Via Hole Filling Technology for High Density, High Aspect Ratio Printed Wiring Boards Using a High Tg, low CTE Plugging Paste
Feb 06, 2023 | Michael Carano
The continued fast pace towards miniaturization is leading circuit board designers to push the envelope on integration density. This trend is driving fabricators to closely look at methods and processes that will enable the move towards sequential lamination and blind and buried via technology. Circuit board fabricators particularly in North America are adopting techniques such as via filling capability with nonconductive, high Tg, low CTE plugging pastes. This paper describes the implementation of the via filling process in a highly effective and reliable fashion for high density, high aspect ratio printed wiring boards. Close attention is paid to use of these via filling materials under high temperature assembly conditions. In addition, via plugging material requirements, equipment considerations and process limitations will be presented. Further, the pros and cons of different filling techniques are discussed. Finally, desmear and metallization techniques to insure adhesion of the plating to the filled via are presented in the context of “Best Practices.”
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