Technical Articles From Atotech

High Phosphorus ENIG – highest resistance against corrosive environment

Jan 10, 2023 | Sven Lamprecht and Petra Backus

Over the past years there has been consistent growth in the use of electroless nickel / immersion gold (ENIG) as a final finish. The finish is now frequently being used for PBGA, CSP, QFP and COB and more recently gathered considerable interest as a low cost under-bump metallization for flip chip bumping application. One of the largest users for this finish has been the telecommunication industry, were millions of square meters of PCBs with ENIG have been successfully used. The nickel layer offers advantages such as multiple soldering cycles and hand reworks without copper dissolution being a factor. The nickel also acts as a reinforcement to improve through-hole and blind micro via thermal integrity. In addition the nickel layer offers advantages such as co-planarity, Al-wire bondability and the use as contact surface for keypads or contact switching. Especially those pads, which are not covered by solder need a protective coating in corrosive environment – such as high humidity or pollutant gas....

Designing a High Performance Electroless Nickel and Immersion Gold to Maximize Highest Reliability

Nov 15, 2020 | Robert Spreemann, Rick Nichols, Sandra Nelle

The latest highest reliability requirements demand a high performance electroless nickel and immersion gold (HP ENIG). The new IPC specification 4552A has refocused the industry with reference to nickel corrosion. The interpretation of the existing specification, that judges corrosion on 3 levels, is complex and if misinterpreted can lead to phantom failures. An obvious way to avoid any potential misinterpretation is to eradicate any evidence of corrosion completely....

Developments in Electroless Copper Processes to Improve Performance in amSAP Mobile Applications

Sep 02, 2020 | Stefanie Bremmert, Laurence Gregoriades, Kay Wurdinger, Thomas Vágó, Tobias Bernhard, Frank Bruning, Roger Massey

With the adoption of Wafer Level Packages (WLP) in the latest generation mobile handsets, the Printed Circuit Board (PCB) industry has also seen the initial steps of High Density Interconnect (HDI) products migrating away from the current subtractive processes towards a more technically adept technique, based on an advanced modified Semi Additive Process (amSAP). This pattern plate process enables line and space features in the region of 20um to be produced, in combination with fully filled, laser formed microvias. However, in order to achieve these process demands, a step change in the performance of the chemical processes used for metallization of the microvia is essential. In the electroless Copper process, the critical activator step often risks cross contamination by the preceding chemistries. Such events can lead to uncontrolled buildup of Palladium rich residues on the panel surface, which can subsequently inhibit etching and lead to short circuits between the final traces. In addition, with more demands being placed on the microvia, the need for a high uniformity Copper layer has become paramount, unfortunately, as microvia shape is often far from ideal, the deposition or "throw" characteristics of the Copper bath itself are also of critical importance. This "high throwing power" is influential elsewhere in the amSAP technique, as it leads to a thinner surface Copper layer, which aids the etching process and enables the ultra-fine features being demanded by today's high end PCB applications. This paper discusses the performance of an electroless Copper plating process that has been developed to satisfy the needs of challenging amSAP applications. Through the use of a radical predip chemistry, the formation, build up and deposition of uncontrolled Pd residues arising from activator contamination has been virtually eradicated. With the adoption of a high throwing power Copper bath, sub 30um features are enabled and microvia coverage is shown to be greatly improved, even in complex via shapes which would otherwise suffer from uneven coverage and risk premature failure in service. Through a mixture of development and production data, this paper aims to highlight the benefits and robust performance of the new electroless Copper process for amSAP applications...

Filling of Microvias and Through Holes by Electrolytic Copper Plating –Current Status and Future Outlook

Mar 12, 2020 | Mustafa Özkök, Sven Lamprecht, Akif Özkök, Dolly Akingbohungbe, Moody Dreiza - Atotech Deutschland GmbH, Alex Stepinski - GreenSource Fabrication LLC

The electronics industry is further progressing in terms of smaller, faster, smarter and more efficient electronic devices. This continuous evolving environment caused the development on various electrolytic copper processes for different applications over the past several decades. (...) This paper describes the reasons for development and a roadmap of dimensions for copper filled through holes, microvias and other copper plated structures on PCBs....

How Detrimental Production Concerns Related to Solder Mask Residues Can Be Countered by Simple Operational Adaptations

Sep 19, 2019 | Rick Nichols, Sandra Heinemann, Gustavo Ramos, Dr. Lars Nothdurft, Hubertus Mertens

The symbiotic relationship between solder masks and selective finishes is not new. The soldermask application is one of the key considerations to ensure a successful application of a selective finish. The selective finish is the final chemical step of the PCB manufacturing process, this is when the panels are at their most valuable and are unfortunately not re-workable. Imperfections are not tolerated, even if they are wholly cosmetic. Quality issues often manifest themselves in the form of a 'ping pong' conversation between the fabricators, the soldermask suppliers and the selective finish suppliers. Without tangible evidence these discussions are difficult to resolve and the selective finish process is usually regarded as responsible.</p> <p>This paper will focus on the chemical characteristics and use them to predict or identify potential issues before they occur rather than specifically name 'critical' soldermasks. It is also the intention of this paper to address the potential of a soldermask to react to common yield hiking practices like UV bumping and oven curing. It is hoped that this awareness will help fabricators to ensure maximum yields by asking the right questions. 'Critical’ soldermasks impact all selective finishes. In this paper, practical experience using immersion tin will be used to highlight the relationship between 'critical' soldermasks and some of the issues seen in the field. The paper will include a novel approach to identify re-deposited volatiles after the reflow....

Soldering Immersion Tin

Apr 10, 2019 | Rick Nichols, Sandra Heinemann

The stimulating impact of the automotive industry has sharpened focus on immersion tin (i-Sn) more than ever before. Immersion tin with its associated attributes, is well placed to fulfill the requirements of such a demanding application. In an environment dominated by reliability, the automotive market not only has very stringent specifications but also demands thorough qualification protocols. Qualification is ultimately a costly exercise. The good news is that i-Sn is already qualified by many tier one OSATs.

The focus of this paper is to generate awareness of the key factors attributed to soldering i-Sn. Immersion tin is not suitable for wire bonding but ultimately suited for multiple soldering applications. The dominant topics of this paper will be IMC formations in relation to reflow cycles and the associated solderability performance. Under contamination free conditions, i-Sn can provide a solderable finish even after multiple reflow cycles. The reflow conditions employed in this paper are typical for lead free soldering environments and the i-Sn thicknesses are approximately 1 μm....

High Throw Electroless Copper - Enabling new Opportunities for IC Substrates and HDI Manufacturing

Apr 20, 2017 | Tobias Sponholz, Lars-Eric Pribyl, Frank Brüning, Robin Taylor

The one constant in electronics manufacturing is change. Moore's Law, which successfully predicted a rate of change at which transistor counts doubled on Integrated Circuits (ICs) at lower cost for decades, is ceding to be an appropriate prediction tool. Increasing technical and economic requirements, deriving from the semiconductor environment, are cascaded down to the printed circuit and in particular to the IC substrate manufacturers. This is both a challenge and an opportunity for IC Substrate manufacturers, when dealing with the demands of the packaging market. (...)

This paper introduces two new electroless copper baths developed for IC substrates manufacturing based on Semi Additive Process (SAP) technology (hereafter referred to as E'less Copper IC) and HDI production (hereafter referred to as E'less Copper HDI) and optimized for high throw into BMVs. An introduction to reliable throwing power measurement methods based on scanning electron microscope (SEM) is given, followed by a compilation and discussion of key performance criteria for each application, namely throwing power, copper adhesion on the substrate, dry film adhesion and reliability....

Effect of Process Variations on Solder Joint Reliability for Nickel-based Surface Finishes

Nov 06, 2014 | Hugh Roberts, Sven Lamprecht, Gustavo Ramos, Christian Sebald

This paper summarizes the results of recent investigations to examine the effect of electroless nickel process variations with respect to Pb-free (Sn-3.0Ag-0.5Cu) solder connections. These investigations included both ENIG and NiPd as surface finishes intended for second level interconnects in BGA applications. Process variations that are suspected to weaken solder joint reliability, including treatment time and pH, were used to achieve differences in nickel layer composition. Immersion gold deposits were also varied, but were directly dependent upon the plated nickel characteristics. In contrast to gold, different electroless palladium thicknesses were independently achieved by treatment time adjustments....

Wire Bonding and Soldering on Enepig and Enep Surface Finishes with Pure Pd-Layers

Oct 11, 2012 | Mustafa Özkök, Joe McGurran, Dieter Metzger, Hugh Roberts

First published in the 2012 IPC APEX EXPO technical conference proceedings. This paper shows the benefits by using a pure palladium Layer in the ENEPIG (Electroless Nickel, Electroless Palladium, Immersion Gold) and ENEP (Electroless Nickel, Electroless P...

Corrosion Resistance of Different PCB Surface Finishes in Harsh Environments

Aug 09, 2012 | Mustafa Özkök, Joe McGurran, Hugh Roberts. Kenneth Lee, Guenter Heinz

First published in the 2012 IPC APEX EXPO technical conference proceedings. Corrosion resistance is becoming one of the most important topics in the electronics industry. Corrosion results in field failures and huge losses, which annually total several bi...

Developments in Fine Line Resist Stripping

Jul 14, 2011 | R. Massey, N. Wood, J. Huang

In this paper, the concept for the next generation of resist stripper solutions is introduced, with specific emphasis upon development of new solutions targeted at the ever demanding fine line applications. The novel formulation used minimises the initial...

Use of Non Etching Adhesion Promoters in Advanced PCB Applications

Jun 16, 2011 | Roger Massey, Adrian Zee

Based on tests carried out with commercially available chemistry, this paper discusses the advantages available through the use of NEAP processes for inner layer bonding and soldermask pretreatment. The process is characterized with a view to high volume ...

Gold Wire Bonding Performance and Reliability of ENEPIG Surface Finishes.

Mar 30, 2011 | Kenneth Lee, Mustafa Özkök, Stefan Schmitz

The expression "multifunctional PCB", as a synonym for a PCB which is applicable with a variety of assembly techniques, is already established on the market. That means the PCB can be used for multiple reflow soldering and multiple assembly techniques lik...